參數(shù)資料
型號(hào)： ICY7C1362C-166BGXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
中文描述： 512K X 18 CACHE SRAM, 3.5 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119
文件頁(yè)數(shù)： 19/31頁(yè)
文件大?。?/td> 432K
代理商： ICY7C1362C-166BGXI
PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 19 of 31
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND ......–0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ....................................–0.5V to VDDQ + 0.5V
DC Input Voltage...................................–0.5V to VDD + 0.5V
Electrical Characteristics
Over the Operating Range
[15, 16]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
DD
V
DDQ
3.3V
– 5%/+10% 2.5V – 5%
to
V
DD
Parameter
V
DD
V
DDQ
Description
Test Conditions
Min.
3.135
3.135
2.375
2.4
2.0
Max.
3.6
V
DD
2.625
Unit
V
V
V
V
V
V
V
V
V
V
V
μ
A
Power Supply Voltage
I/O Supply Voltage
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V, V
DD
= Min., I
OH
= –4.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OH
= –1.0 mA
V
DDQ
= 3.3V, V
DD
= Min., I
OL
= 8.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OL
= 1.0 mA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
GND
≤
V
I
≤
V
DDQ
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
0.4
0.4
V
IH
Input HIGH Voltage
[15]
2.0
1.7
–0.3
–0.3
–5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.8
0.7
5
V
IL
Input LOW Voltage
[15]
I
X
Input Load Current
except ZZ and MODE
Input Current of MODE
Input = V
SS
Input = V
DD
Input = V
SS
Input = V
DD
GND
≤
V
I
≤
V
DDQ,
Output Disabled
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
–30
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
mA
mA
mA
5
Input Current of ZZ
–5
30
5
250
220
180
130
120
110
30
I
OZ
I
DD
Output Leakage Current
V
DD
Operating Supply
Current
–5
4.0-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
4.0-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
All speeds
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
f = f
MAX
= 1/t
CYC
I
SB2
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
– 0.3V,
f = 0
V
DD
= Max, Device Deselected, or
V
IN
≤
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
= 1/t
CYC
I
SB3
4.0-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
All Speeds
120
110
100
40
mA
mA
mA
mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = 0
Shaded areas contain advance information.
Notes:
15.Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC) > –2V (Pulse width less than t
CYC
/2).
16.T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
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