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參數(shù)資料
| 型號： | ICY7C1362C-166BGXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大小： | 432K |
| 代理商： | ICY7C1362C-166BGXI |
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PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 14 of 31
TAP AC Switching Characteristics
Over the Operating Range
[10, 11]
3.3V TAP AC Test Conditions
Input pulse levels................................................ V
SS
to 3.3V
Input rise and fall times..................... ..............................1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels
...........................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
Parameter
Clock
t
TCYC
t
TF
t
TH
t
TL
Output Times
t
TDOV
t
TDOX
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
ns
20
25
25
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
5
ns
ns
0
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
TDO
1.5V
20pF
Z = 50
W
50
W
TDO
1.25V
20pF
Z = 50
W
50
W
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)
[12]
Parameter
V
OH1
Description
Output HIGH Voltage
Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
V
V
V
V
V
I
OH
= –4.0 mA
I
OH
= –1.0 mA
I
OH
= –100 μA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
OH2
Output HIGH Voltage
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
I
OL
= 8.0 mA
0.4
0.4
Notes:
10.t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. t
R
/t
F
= 1ns.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICY7C1362C-166BZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| ICY7C1367B-166BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM |
| ICY7C1373C-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture |
| ICY7C1373D-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| ICY7C1373D-100BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
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