參數(shù)資料
型號： IBM25EMPPC603EFG-100
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240
封裝： 32 X 32 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, FP-240
文件頁數(shù)： 28/42頁
文件大?。?/td> 509K
代理商： IBM25EMPPC603EFG-100
34
603e and EM603e Hardware Specification
1.8.2 PLL Power Supply Filtering
The AVdd power signal is provided on the 603e and EM603e to provide power to the clock generation
phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal
must be ltered using a circuit similar to the one shown in Figure 15. The circuit must be placed as close
as possible to the AVdd pin to ensure that it lters out as much noise as possible. The 0.1
F capacitor
must be closest to the AVdd pin, followed by the 10
F capacitor, then nally the 10 resistor nearer to
Vdd. These traces must be kept short and direct.
Figure 15. PLL Power Supply Filter Circuit
1.8.3 Decoupling Recommendations
Due to the 603e’s and EM603e’s dynamic power management feature, large address and data buses, and
high operating frequencies, the 603e and EM603e can generate transient power surges and high frequency
noise in their power supplies, especially while driving large capacitive loads. This noise must be prevented
from reaching other components in the 603e and EM603e systems, and the 603e and EM603e themselves
require a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each Vdd and OVdd pin of the 603e and EM603e. It is also
recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, and GND
power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10
F to provide both high- and low-frequency
ltering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values
for the Vdd pins—220 pF (ceramic), 0.01
F (ceramic), and 0.1 F (ceramic). Suggested values for the
OVdd pins—0.01
F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount
technology) capacitors should be used to minimize lead inductance.
0011
PLL bypass
1111
Clock off
Notes:
1. Some PLL congurations may select bus, CPU, or VCO frequencies which are not supported; see
Section 1.4.2.1, “Clock AC Specications,” for valid SYSCLK and VCO frequencies.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and
the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specications given in this document do not apply in PLL-bypass mode.
3. In clock-off mode, no clocking occurs inside the 603e and EM603e regardless of the SYSCLK input.
Table 14. PowerPC 603e and EM603e Processor PLL Configuration for PID7v and PID7t (Continued)
PLL_CFG[0–3]
CPU Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
25 MHz
Bus
33.33
MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67
MHz
Bus
75 MHz
Vdd
AVdd
10
10
F
0
.1
F
GND
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