參數(shù)資料
型號: IBM25EMPPC603EFG-100
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240
封裝: 32 X 32 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, FP-240
文件頁數(shù): 27/42頁
文件大小: 509K
代理商: IBM25EMPPC603EFG-100
603e and EM603e Hardware Specification
33
The PLL conguration for the PID7v and PID7t is shown in Table 14 for nominal frequencies.
1111
Clock off
Notes:
1. PLL_CFG[0-3] settings not listed are reserved.
2. Some PLL congurations may select bus, core, or VCO frequencies which are not useful, not supported, or
not tested for by the 603e and EM603e; see Section 1.4.2.1, “Clock AC Specications,” for valid SYSCLK
and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and
the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specications given in this document do not apply in PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the 603e and EM603e regardless of the SYSCLK input.
Table 14. PowerPC 603e and EM603e Processor PLL Configuration for PID7v and PID7t
PLL_CFG[0–3]
CPU Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
25 MHz
Bus
33.33
MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67
MHz
Bus
75 MHz
0100
2x
———133
(266)
150
(300)
0101
2x
4x
————
0110
2.5x
2x
125
(250)
150
(300)
166
(333)
187
(375)
1000
3x
2x
120
(240)
150
(300)
180
(360)
200
(400)
225
(450)
1110
3.5x
2x
140
(280)
175
(350)
210
(420)
233
(466)
1010
4x
2x
133
(266)
160
(320)
200
(400)
240
(480)
0111
4.5x
2x
150
(300)
180
(360)
225
(450)
——
1011
5x
2x
125
(250)
166
(333)
200
(400)
———
1001
5.5x
2x
137
(275)
183
(366)
220
(440)
———
1101
6x
2x
150
(300)
200
(400)
240
(480)
———
Table 13. PowerPC 603e and EM603e Microprocessor PLL Configuration for PID6 (Continued)
PLL_CFG
[0–3]1
CPU Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multi-
plier
Core-to
VCO
Multi-
plier
Bus
16.67
MHz
Bus
20
MHz
Bus
25
MHz
Bus
33.33
MHz
Bus
40
MHz
Bus
50
MHz
Bus
60
MHz
Bus
66.67
MHz
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