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參數(shù)資料
| 型號： | IBM13M64734HCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動態(tài)RAM模塊) |
| 中文描述： | 64米× 72雙銀行注冊內(nèi)存模塊（64米× 72 2組帶寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/22頁 |
| 文件大小： | 392K |
| 代理商： | IBM13M64734HCA |
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 22
06K8049.H03530
5/00
Serial Presence Detect (Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Notes
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM
04
3
Number of Row Addresses on Assembly
13
0D
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Banks
2
02
6 - 7
Data Width of Assembly
x72
4800
8
Assembly Voltage Interface Levels
LVTTL
01
9
SDRAM Device Cycle Time (CL = 3)
7.5ns
75
1, 2
10
SDRAM Device Access Time from Clock at CL=3
5.4ns
54
11
Assembly Error Detection/Correction Scheme
ECC
02
12
Assembly Refresh Rate/Type
SR/1X(7.8125
μ
s)
82
13
SDRAM Device Width
x8
08
14
Error Checking SDRAM Device Width
x8
08
15
SDRAM Device Attr: Min Clk Delay, Random Col Access
1 Clock
01
16
SDRAM Device Attributes: Burst Lengths Supported
1,2,4,8
0F
17
SDRAM Device Attributes: Number of Device Banks
4
04
18
SDRAM Device Attributes: CAS Latency
2, 3
06
19
SDRAM Device Attributes: CS Latency
0
01
20
SDRAM Device Attributes: WE Latency
0
01
21
SDRAM Module Attributes
Registered/Buffered
with PLL
IF
22
SDRAM Device Attributes: General
Write-1/Read Burst,
Precharge All,
Auto-Precharge
0E
23
Minimum Clock Cycle at CLX-1 (CL = 2)
15.0ns
1F
1, 2
24
Maximum Data Access Time (t
AC
) from Clock at CLX-1 (CL = 2)
9.0ns
90
25
Minimum Clock Cycle Time at CLX-2 (CL = 1)
N/A
00
26
Maximum Data Access Time (t
AC
) from Clock at CLX-2 (CL = 1)
N/A
00
27
Minimum Row Precharge Time (t
RP
)
20.0ns
14
28
Minimum Row Active to Row Active delay (t
RRD
)
15.0ns
0F
29
Minimum RAS to CAS delay (t
RCD
)
20.0ns
14
30
Minimum RAS Pulse width (t
RAS
)
45.0ns
2D
31
Module Bank Density
256MB
40
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock
cycles] + 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 7.5ns (133 MHz).
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex).
7. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
9. These values apply to PC100 applications only.
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