參數(shù)資料
型號(hào)： IBM13M64734HCA
廠商： IBM Microeletronics
英文描述： 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動(dòng)態(tài)RAM模塊)
中文描述： 64米× 72雙銀行注冊(cè)內(nèi)存模塊（64米× 72 2組帶寄存同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 5/22頁(yè)
文件大?。?/td> 392K
代理商： IBM13M64734HCA
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
06K8049.H03530
5/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 22
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0 - CK3
Input
Pulse
Positive
Edge
The system clock inputs. All the SDRAM inputs are sampled on the rising edge of
their associated clock. CK0 drives the PLL. CK1, CK2, and CK3 are terminated.
CKE0
Input
Level
Active High
Activates the SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode, the Suspend
mode, or the Self Refresh mode.
S0-S3
Input
Pulse
Active Low
Enables the associated SDRAM command decoder when low and disables the com-
mand decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
RAS, CAS
WE
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
BA0, 1
Input
Level
—
Selects which SDRAM bank of four is activated.
A0 - A9
A10/AP
A11, A12
Input
Level
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-
RA12) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 define the column address (CA0-
CA9) when sampled at the rising clock edge. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If
AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be pre-
charged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to con-
trol which bank(s) to precharge. If AP is high, all banks will be precharged regardless
of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank
to precharge.
DQ0 - DQ63,
CB0 - CB7
Input
Output
Level
—
Data and Check Bit Input/Output pins.
DQMB0 -
DQMB7
Input
Pulse
Active High
The Data Input/Output masks, associated with one data byte, place the DQ buffers in
a high-impedance state when sampled high. In Read mode, DQMB has a latency of
two clock cycles in Buffered mode or three clock cycles in Registered mode, and con-
trols the output buffers like an output enable.
In Write mode, DQMB has a zero clock latency in Buffered mode and a latency of
one clock cycle in Registered mode. In this case, DQMB operates as a byte mask by
allowing input data to be written if it is low but blocking the write operation if it is high.
V
DD
, V
SS
Supply
—
Power and ground for the module.
REGE
Input
Level
Active High
(Register
Mode
Enable)
The Register Enable pin must be held high to permit the DIMM to operate in “regis-
tered” mode (signals re-driven to SDRAMs when clock rises, and held valid until next
rising clock).
SA0 - 2
Input
Level
—
These signals are tied at the system planar to either V
SS
or V
DD
to configure the
serial SPD EEPROM.
SDA
Input
Output
Level
—
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A
resistor must be connected from the SDA bus line to V
DD
to act as a pullup.
SCL
Input
Pulse
—
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
WP
Input
Level
Active High
This signal is pulled low on the DIMM to enable data to be written into the last 128
bytes of the SPD EEPROM.
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