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參數(shù)資料
| 型號： | IBM13M64734HCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動態(tài)RAM模塊) |
| 中文描述： | 64米× 72雙銀行注冊內(nèi)存模塊（64米× 72 2組帶寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 392K |
| 代理商： | IBM13M64734HCA |
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
06K8049.H03530
5/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 22
Read Cycle
Symbol
Parameter
-75A
Units
Notes
Min.
3.1
0.6
3.6
3
Max.
—
—
6.6
—
t
OH
t
LZ
t
HZ3
t
DQZ
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
ns
ns
ns
CLK
1
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-75A
Units
Min.
1.75
1.05
15
5
1
Max.
—
—
—
—
—
t
DS
t
DH
t
DPL
t
DAL3
t
DQW
Data In Setup Time
Data In Hold Time
Data input to Precharge
Data in to Active Delay (CAS Latency = 3)
DQM Write Mask Latency
ns
ns
ns
CLK
CLK
Presence Detect Read and Write Cycle
Symbol
Parameter
-75A
Units
Notes
Min.
—
—
0.3
4.7
4
4.7
4
4.7
0
250
—
—
4.7
300
—
Max.
100
100
3.5
—
—
—
—
—
—
—
1
300
—
—
15
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
DH
t
WR
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
KHz
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
ns
ms
1
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
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