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參數(shù)資料
| 型號： | IBM13M64734HCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動態(tài)RAM模塊) |
| 中文描述： | 64米× 72雙銀行注冊內(nèi)存模塊（64米× 72 2組帶寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 392K |
| 代理商： | IBM13M64734HCA |
06K8049.H03530
5/00
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 22
Features
168-Pin Registered 8-Byte Dual In-Line Memory
Module
64Mx72 Synchronous DRAM DIMM
Performance:
Intended for 100MHz and 133MHz applications
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.3V Power Supply
Single Pulsed RAS interface
SDRAMs have four internal banks
Module has two physical banks
Fully Synchronous to positive Clock Edge
Programmable Operation:
- DIMM CAS Latency: 3, 4 (Registered mode)
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
Data Mask for Byte Read/Write control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
Suspend Mode and Power Down Mode
13/10/2 Addressing (Row/Column/Bank)
8192 refresh cycles distributed across 64ms
Card size: 5.25" x 0.157" x 1.70"
Gold contacts
SDRAMs in TSOP
Serial Presence Detect with Write protect
Description
IBM13M64734HCA is a registered 168-Pin Synchro-
nous DRAM Dual In-Line Memory Module (DIMM)
organized as a 64Mx72 high-speed memory array
and is configured as two 32M x 72 physical banks.
The DIMM uses eighteen 32Mx8 SDRAMs in 400
mil TSOP packages. The DIMM achieves high-
speed data-transfer rates of 100MHz and 133MHz
by employing a prefetch/pipeline hybrid architecture
that synchronizes the output data to a system clock.
The DIMM is intended for use in applications operat-
ing at 100MHz and 133MHz memory bus speeds. All
control and address signals are re-driven through
registers to the SDRAM devices. The DIMM oper-
ates in registered mode (REGE pin tied high), during
which the control/address input signals are latched
in the register on one rising clock edge and sent to
the SDRAM devices on the following rising clock
edge (data access is delayed by one clock).
A phase-lock loop (PLL) on-board the DIMM re-
drives the clock signals to the SDRAM devices and
registers to minimize system clock loading. (CK0 is
connected to the PLL, and CK1, CK2, and CK3 are
terminated on the DIMM.) A single clock enable
(CKE0) controls all devices on the DIMM, enabling
the use of SDRAM power-down modes.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must be
programmed into the DIMM by address inputs A0-A9
using the mode register set cycle. The DIMM CAS
latency is one clock later due to the address and
control signals being clocked to the SDRAM
devices.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked by the DIMM manufacturer.
The last 128 bytes are available to the customer and
can be write protected by providing a high level to
pin 81 on the DIMM. An on-board pulldown resistor
keeps this in the write-enable mode.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint.
-75A
4
Units
DIMM CAS Latency
f
CK
Clock Frequency
f
CK
Clock Cycle
t
AC
Clock Access
133
7.5
5.65
100
10
5.65
MHz
ns
ns
.
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