參數(shù)資料
型號(hào)： IBM13M64734HCA
廠商： IBM Microeletronics
英文描述： 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動(dòng)態(tài)RAM模塊)
中文描述： 64米× 72雙銀行注冊(cè)內(nèi)存模塊（64米× 72 2組帶寄存同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 13/22頁(yè)
文件大?。?/td> 392K
代理商： IBM13M64734HCA
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
06K8049.H03530
5/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 22
Clock and Clock Enable Parameters
Symbol
Parameter
-75A max. (Device CL,
t
RCD
, t
RP
= 3, 3, 3)
Units
Notes
Min.
Max.
t
CK4
t
AC4
t
CKH
t
CKL
t
CES
t
CEH
t
SB
t
T
Clock Cycle Time, DIMM CAS Latency = 4
7.5
1000
ns
1
Clock Access Time, DIMM CAS Latency = 4
—
5.65
ns
1, 2
Clock High Pulse Width
2.5
—
ns
3
Clock Low Pulse Width
2.5
—
ns
3
Clock Enable Setup Time
1.65
—
ns
1
Clock Enable Hold Time
0.35
—
ns
1
Power Down Mode Entry Time
0
7.5
ns
Transition Time (Rise and Fall)
0.5
10
ns
1. DIMM CAS latency = device CL [clock cycles] + 1 for Register mode.
2. Access time is measured at 1.4V. See AC output load circuit.
3. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse
width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
相關(guān)PDF資料
PDF描述
IBM13M8734HCB 8M x 72 1 Bank Registered SDRAM Module with PLL(8M x 72 1組帶鎖相環(huán)的寄存同步動(dòng)態(tài)RAM模塊)
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