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參數(shù)資料
| 型號(hào)： | IBM13M8734HCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 1 Bank Registered SDRAM Module with PLL(8M x 72 1組帶鎖相環(huán)的寄存同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 8米× 72 1帶鎖相環(huán)銀行注冊(cè)內(nèi)存模塊（8米× 72 1組帶鎖相環(huán)的寄存同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 325K |
| 代理商： | IBM13M8734HCB |
IBM13M8734HCB
Preliminary
8M x 72 1 Bank Registered SDRAM Module with PLL
08J0514.E24449
4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 19
Features
168-Pin Registered 8-Byte Dual In-Line Memory
Module
8Mx72 Synchronous DRAM DIMM
Performance (Registered Mode):
Intended for 66/100MHz and PC100 applications
All inputs and outputs are LVTTL (3.3V) compati-
ble
Single 3.3V
±
0.3V Power Supply
Single Pulsed RAS interface
SDRAMs have four internal banks
Module has one physical bank
Fully Synchronous to positive Clock Edge
Programmable Operation:
- DIMM CAS Latency:3, 4 (Registered mode)
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8, Full-Page (Full-Page
supports Sequential burst only)
- Operation: Burst Read and Write
or Multiple Burst Read with Single Write
Data Mask for Byte Read/Write control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
Suspend Mode and Power Down Mode
12/9/2 Addressing (Row/Column/Bank)
4096 refresh cycles distributed across 64ms
Card size: 5.25" x 1.5" x 0.157"
Gold contacts
SDRAMs in TSOP - Type II Package
Serial Presence Detect with Write protect feature
Description
IBM13M8734HCB is a registered 168-Pin Synchro-
nous DRAM Dual In-Line Memory Module (DIMM)
organized as an 8Mx72 high-speed memory array.
The DIMM uses nine 8Mx8 SDRAMs in 400 mil
TSOP packages. The DIMM achieves high-speed
data-transfer rates of up to 100 MHz by employing a
prefetch/pipeline hybrid architecture that synchro-
nizes the output data to a system clock.
The DIMM is intended for use in applications operat-
ing from 66MHz to 100MHz, PC100, memory bus
speeds, and/or heavily loaded bus applications. All
control and address signals are re-driven through
registers to the SDRAM devices. The con-
trol/address input signals are latched in the register
on one rising clock edge and sent to the SDRAM
devices on the following rising clock edge (data
access is delayed by one clock).
A phase-lock loop (PLL) on the DIMM is used to re-
drive the clock signals to the SDRAM devices to min-
imize system clock loading. (CK0 is connected to the
PLL, and CK1, CK2, and CK3 are terminated on the
DIMM.) A single clock enable (CKE0) controls all
devices on the DIMM, enabling the use of SDRAM
power-down modes.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must be
programmed into the DIMM by address inputs A0-A9
using the mode register set cycle. The DIMM CAS
latency when operated in buffered mode is the same
as the device CAS latency as specified in the SPD
EEPROM. The DIMM CAS latency when operated in
registered mode is one clock later due to the address
and control signals being clocked to the SDRAM
devices.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked by the DIMM manufacturer.
The last 128 bytes are available to the customer and
may be write protected by providing a high level to
pin 81 on the DIMM. (An on-board pulldown resistor
keeps this in the write-enable mode.)
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint.
-10
-360
(PC100)
4
100
10
7.7
Units
DIMM CAS Latency
Clock Frequency
Clock Cycle
Clock Access Time
3
f
CK
t
CK
t
AC
66
15
9.7
MHz
ns
ns
IBM11M4730C4M x 72 E12/10, 5.0V, Au.
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