參數(shù)資料
型號(hào)： IBM13M8734HCB
廠商： IBM Microeletronics
英文描述： 8M x 72 1 Bank Registered SDRAM Module with PLL(8M x 72 1組帶鎖相環(huán)的寄存同步動(dòng)態(tài)RAM模塊)
中文描述： 8米× 72 1帶鎖相環(huán)銀行注冊(cè)內(nèi)存模塊（8米× 72 1組帶鎖相環(huán)的寄存同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 8/19頁(yè)
文件大?。?/td> 325K
代理商： IBM13M8734HCB
IBM13M8734HCB
8M x 72 1 Bank Registered SDRAM Module with PLL
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 19
08J0514.E24449
4/98
30
Minimum RAS Pulse width (t
RAS
)
-360, -365, -370
50.0ns
32
-10
60.0ns
3C
31
Module Bank Density
64MB
10
32
Address and Command Setup Time Before
Clock
-360, -365, -370
2.0ns
20
-10
Undefined
00
33
Address and Command Hold Time After
Clock
-360, -365, -370
1.0ns
10
-10
Undefined
00
34
Data Input Setup Time Before Clock
-360, -365, -370
2.0ns
20
-10
Undefined
00
35
Data Input Hold Time After Clock
-360, -365, -370
1.0ns
10
-10
Undefined
00
36 - 61
Reserved
Undefined
00
62
SPD Revision
-360, -365, -370
PC100 1.2A
12
-10
01
01
63
Checksum for bytes 0 - 62
Checksum Data
cc
3
64 - 71
Manufacturers’ JEDEC ID Code
IBM
A400000000000000
72
Assembly Manufacturing Location
Toronto, Canada
91
Vimercate, Italy
53
73 - 90
Assembly Part Number
-360
ASCII ‘13M8734HC”R”-360T’
31334D383733344843rr2D303
63054202020
4, 5
-365
ASCII ‘13M8734HC”R”-365T’
31334D383733344843rr2D303
63554202020
-370
ASCII ‘13M8734HC”R”-370T’
31334D383733344843rr2D303
73054202020
-10
ASCII ‘13M8734HC”R”-10T’
31334D383733344843rr2D313
05420202020
91 - 92
Assembly Revision Code
“R” plus ASCII blank
rr20
5
93 - 94
Assembly Manufacturing Date
Year/Week Code
yyww
6, 7
95 - 98
Assembly Serial Number
Serial Number
ssssssss
8
99 - 125 Reserved
Undefined
Not Specified
126
Module Supports this Clock Frequency
-360, -365, -370
100MHz
64
-10
66MHz
66
127
Attributes for clock frequency defined in
Byte 126
-360, -365, -370
CLK0, CL=3, ConAP
85
-10
CL = 2, 3
06
128 -
255
Open for Customer Use
Undefined
00
Serial Presence Detect (Part 2 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry (Hexa-
decimal)
Notes
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles]
+ 1 = DIMM CAS latency).
2. Minimum application clock cycle time for the -360, -365, and -370 is 10ns (100MHz), and for -10 is 15ns (66MHz).
3. cc = Checksum Data byte, 00-FF (Hex)
4. “R” = Alphanumeric revision code, A-Z, 0-9
5. rr = ASCII coded revision code byte “R”
6. ww = Binary coded decimal week code, 01-53 (Decimal)
01-35 (Hex)
7. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex)
8. ss = Serial number data byte, 00-FF (Hex)
相關(guān)PDF資料
PDF描述
IBM13M8734HCC 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
IBM13M8734HCD 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
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