參數(shù)資料
型號: IBM13M64734HCA
廠商: IBM Microeletronics
英文描述: 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動態(tài)RAM模塊)
中文描述: 64米× 72雙銀行注冊內(nèi)存模塊(64米× 72 2組帶寄存同步動態(tài)內(nèi)存模塊)
文件頁數(shù): 16/22頁
文件大小: 392K
代理商: IBM13M64734HCA
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 22
06K8049.H03530
5/00
Wiring and Topology
This section contains the information needed to understand the timing relationships presented in AC Charac-
teristics beginning on page 12. Each timing parameter is measured at the first receiving device (SDRAM DQ
pin for data input, register input pin for address and control, and PLL Clk input pin for clock). This section will
enable the user to understand the pin numbers on the DIMM, the net structures, and the loading associated
with these devices. For detailed timing analysis, contact the IBM Marketing Representative for simulation
models. Modeling is strongly recommended to determine delay adders of the entire net structure.
Pin Assignments for the 256Mbit SDRAM Planar Component
TOP VIEW
54-pin Plastic TSOP(II) 400mil
16Mbit x 8 I/O x 4 Bank
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS
BS0
BS1
A10/AP
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
A0
A1
A2
A3
V
DD
相關(guān)PDF資料
PDF描述
IBM13M8734HCB 8M x 72 1 Bank Registered SDRAM Module with PLL(8M x 72 1組帶鎖相環(huán)的寄存同步動態(tài)RAM模塊)
IBM13M8734HCC 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動態(tài)RAM模塊)
IBM13M8734HCD 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動態(tài)RAM模塊)
IBM13N16644HCB 16M x 64 Two-Bank Unbuffered SDRAM Module(16M x 64 2組不帶緩沖同步動態(tài)RAM模塊)
IBM13N16734HCB 16M x 72 Two-Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動態(tài)RAM模塊)
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