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參數(shù)資料
| 型號： | IBM13M32734JCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Two Bank Registered/Buffered SDRAM Module(64M x 64 2組不帶緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置兩個銀行的注冊/緩沖內(nèi)存模組（64米× 64 2組不帶緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 529K |
| 代理商： | IBM13M32734JCA |
IBM13M32734JCA
32M x 72 Two Bank Registered/Buffered SDRAM Module
09K3883.F38743
4/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 20
Serial Presence Detect (Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
04
0C
0A
02
Note
s
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Assembly Voltage Interface Levels
SDRAM Device Cycle Time (CL = 3)
SDRAM Device Access Time from Clock at CL=3
Assembly Error Detection/Correction Scheme
Assembly Refresh Rate/Type
SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min Clk Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latency
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
128
256
SDRAM
12
10
2
6 - 7
8
9
10
11
12
13
14
15
16
17
18
19
20
x72
LVTTL
10.0ns
6.0ns
ECC
4800
01
A0
60
02
80
08
08
1, 2
SR/1X(15.625us)
x8
x8
1 Clock
01
8F
04
06
01
01
1,2,4,8, Full Page
4
2, 3
0
0
Registered/Buffered with
PLL
Write-1/Read Burst, Pre-
charge All, Auto-Precharge
10.0ns
15.0ns
6.0ns
9.0ns
N/A
21
SDRAM Module Attributes
IF
22
SDRAM Device Attributes: General
0E
23
Minimum Clock Cycle at CLX-1 (CL = 2)
-260
-360
-260
-360
A0
F0
60
90
00
1, 2
24
Maximum Data Access Time (t
AC
) from Clock at
CLX-1 (CL = 2)
25
Minimum Clock Cycle Time at CLX-2 (CL = 1)
Maximum Data Access Time (t
AC
) from Clock at CLX-2 (CL =
1)
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse width (t
RAS
)
26
N/A
00
27
20.0ns
14
28
20.0ns
14
29
20.0ns
14
30
50.0ns
32
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock
cycles] + 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 10ns for -260 CL=2 and for -360 CL=3 and 15ns for -360 CL=2.
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex).
7. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
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