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參數(shù)資料
| 型號： | IBM13M32734JCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Two Bank Registered/Buffered SDRAM Module(64M x 64 2組不帶緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置兩個銀行的注冊/緩沖內(nèi)存模組（64米× 64 2組不帶緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 529K |
| 代理商： | IBM13M32734JCA |
IBM13M32734JCA
32M x 72 Two Bank Registered/Buffered SDRAM Module
09K3883.F38743
4/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 20
Common Parameters
Symbol
Parameter
-260
-360
Units
Notes
Min.
Max.
Min.
Max.
t
CS
Command Setup Time
Registered
2.0
—
2.0
—
ns
1, 2
Buffered
7.4
—
7.4
—
ns
t
CH
Command Hold Time
Registered
1.1
—
1.0
—
ns
1, 2
Buffered
0.0
—
0.0
—
ns
t
AS
Address and Bank Select Setup Time
Registered
2.0
—
2.0
—
ns
1, 2
Buffered
7.4
—
7.4
—
ns
t
AH
Address and Bank Select Hold Time
Registered
1.0
—
1.0
—
ns
1, 2
Buffered
0.0
—
0.0
—
ns
t
RCD
RAS to CAS Delay
20
—
20
—
ns
1
t
RC
Bank Cycle Time
70
—
70
—
ns
1
t
RAS
Active Command Period
50
100000
50
100000
ns
1
t
RP
Precharge Time
20
—
20
—
ns
1
t
RRD
Bank to Bank Delay Time
20
—
20
—
ns
1
t
CCD
CAS to CAS Delay Time (Same Bank)
1
—
1
—
CLK
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the num-
ber of clock cycles = specified value of timing/clock period (count fractions as a whole number).
2. The set up and hold times refer to the addition of the register. Note that although the Buffered set up times appear much greater,
there is no additional clock cycle as there is in Registered mode.
Mode Register Set Cycle
Symbol
Parameter
-260
-360
Units
Notes
Min.
Max.
Min.
Max.
t
RSC
Mode Register Set Cycle Time
2
—
2
—
CLK
1
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the num-
ber of clock cycles = specified value of timing/clock period (count fractions as a whole number).
Refresh Cycle
Symbol
Parameter
-260
-360
Units Notes
Min.
Max.
Min.
Max.
t
REF
Refresh Period
—
64
—
64
ms
1
1. 4096cycles.
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