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參數(shù)資料
| 型號： | IBM13M32734JCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Two Bank Registered/Buffered SDRAM Module(64M x 64 2組不帶緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置兩個銀行的注冊/緩沖內存模組（64米× 64 2組不帶緩沖同步動態(tài)內存模塊） |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 529K |
| 代理商： | IBM13M32734JCA |
IBM13M32734JCA
32M x 72 Two Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 20
09K3883.F38743
4/00
Read Cycle
Symbol
Parameter
-260
-360
Units
Notes
Min.
Max.
Min.
Max.
t
OH
Data Out Hold Time
3.6
—
3.6
—
ns
t
LZ
Data Out to Low Impedance Time
0.6
—
0.6
—
ns
t
HZ3
Data Out to High Impedance Time
3.6
7.2
3.5
7.2
ns
1
t
HZ2
Data Out to High Impedance Time
3.6
7.2
3.6
9.2
ns
1
t
DQZ
DQM Data Out Disable Latency
Registered
3
—
3
—
CLK
Buffered
2
—
2
—
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-260
-360
Units
Min.
Max.
Min.
Max.
t
DS
Data In Setup Time
2.1
—
2.1
—
ns
t
DH
Data In Hold Time
1.6
—
1.6
—
ns
t
DPL
Data input to Precharge
Registered
10
—
10
—
ns
Buffered
20
—
20
—
ns
t
DAL3
Data input to Active, CL = 3
Registered
4
—
4
—
CLK
Buffered
5
—
5
—
CLK
t
DAL2
Data input to Active CL = 2
Registered
4
—
4
—
CLK
Buffered
5
—
5
—
CLK
t
DQW
DQM Write Mask Latency
Registered
1
—
1
—
CLK
Buffered
0
—
0
—
CLK
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