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參數(shù)資料
| 型號： | IBM13M32734JCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Two Bank Registered/Buffered SDRAM Module(64M x 64 2組不帶緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置兩個銀行的注冊/緩沖內(nèi)存模組（64米× 64 2組不帶緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 529K |
| 代理商： | IBM13M32734JCA |
IBM13M32734JCA
32M x 72 Two Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 20
09K3883.F38743
4/00
Clock and Clock Enable Parameters
Symbol
Parameter
-260 max.
(Device CL,
t
RCD
, t
RP
= 2, 2, 2)
-360 max.
(Device CL,
t
RCD
, t
RP
= 3, 2, 2)
Units
Notes
Min.
Max.
Min.
Max.
t
CK4
Clock Cycle Time, DIMM CAS Latency = 4
Registered
10
1000
10
1000
ns
1
t
CK3
Clock Cycle Time, DIMM CAS Latency = 3
Registered
10
1000
15
1000
ns
1
Buffered
10
1000
10
1000
ns
t
CK2
Clock Cycle Time, DIMM CAS Latency = 2
Buffered
10
1000
15
1000
ns
1
t
AC4
Clock Access Time, DIMM CAS Latency = 4
Registered
—
7.2
—
7.2
ns
1, 2
t
AC3
Clock Access Time, DIMM CAS Latency = 3
Registered
—
7.2
—
10.2
ns
1, 2
Buffered
—
7.2
—
7.2
ns
t
AC2
Clock Access Time, DIMM CAS Latency = 2
Buffered
—
7.2
—
10.2
ns
1, 2
t
CKH
Clock High Pulse Width
3
—
3
—
ns
3
t
CKL
Clock Low Pulse Width
3
—
3
—
ns
3
t
CES
Clock Enable Setup Time
Registered
2.0
—
2.0
—
ns
1
Buffered
7.2
—
7.2
—
ns
t
CEH
Clock Enable Hold Time
Registered
1.0
—
1.0
—
ns
1
Buffered
0.2
—
0.2
—
ns
t
SB
Power down mode Entry Time
0
10
0
10
ns
t
T
Transition Time (Rise and Fall)
0.5
10
0.5
10
ns
1. DIMM CAS latency = device CL [clock cycles] + 1 for Register mode; DIMM CAS latency is one clock less for Buffer mode.
2. Access time is measured at 1.4V. See AC output load circuit.
3. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse
width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
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