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| 型號： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 37/58頁 |
| 文件大小： | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
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HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
42
04212008-66HT-ZLFE
1)
V
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
DQ low impedance time from CK/CK
t
LZ.DQ
2×
t
AC.MIN
t
AC.MAX
2×
t
AC.MIN
t
AC.MAX
ps
DQS/DQS low-impedance time from
CK / CK
t
LZ.DQS
t
AC.MIN
t
AC.MAX
t
AC.MIN
t
AC.MAX
ps
MRS command to ODT update delay
t
MOD
0
12
0
12
ns
Mode register set command cycle
time
t
MRD
2—
nCK
OCD drive mode output delay
t
OIT
0
12
0
12
ns
DQ/DQS output hold time from DQS
t
QH
t
HP – tQHS
—
t
HP – tQHS
—ps
DQ hold skew factor
t
QHS
—
300
—
340
ps
Average periodic refresh Interval
t
REFI
—7.8
μs
—3.9
μs
Auto-Refresh to Active/Auto-Refresh
command period
t
RFC
127.5
—
127.5
—
ns
Read preamble
t
RPRE
0.9
1.1
0.9
1.1
t
CK.AVG
Read postamble
t
RPST
0.4
0.6
0.4
0.6
t
CK.AVG
Active to active command period for
1KB page size products
t
RRD
7.5
—
7.5
—
ns
Active to active command period for
2KB page size products
t
RRD
10
—
10
—
ns
Internal Read to Precharge command
delay
t
RTP
7.5
—
7.5
—
ns
Write preamble
t
WPRE
0.35
—
0.35
—
t
CK.AVG
Write postamble
t
WPST
0.4
0.6
0.4
0.6
t
CK.AVG
Write recovery time
t
WR
15
—
15
—
ns
Internal write to read command delay
t
WTR
7.5
—
7.5
—
ns
Exit active power down to read
command
t
XARD
2—
nCK
Exit active power down to read
command (slow exit, lower power)
t
XARDS
8 – AL
—
7 – AL
—
nCK
Exit precharge power-down to any
command
t
XP
2—
nCK
Exit self-refresh to a non-read
command
t
XSNR
t
RFC +10
—
t
RFC +10
—
ns
Exit self-refresh to read command
t
XSRD
200
—
200
—
nCK
Write command to DQS associated
clock edges
WL
RL – 1
RL–1
nCK
Parameter
Symbol
DDR2–800
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Min.
Max.
Min.
Max.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
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