參數(shù)資料
型號(hào)： HYB18T1G800C4F-3
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, 0.45 ns, PBGA60
封裝： GREEN, PLASTIC, TFBGA-60
文件頁(yè)數(shù)： 24/58頁(yè)
文件大?。?/td> 1898K
代理商： HYB18T1G800C4F-3
HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
30
04212008-66HT-ZLFE
FIGURE 4
Single-ended AC Input Test Conditions Diagram
TABLE 25
Differential DC and AC Input and Output Logic Levels
FIGURE 5
Differential DC and AC Input and Output Logic Levels Diagram
Symbol
Parameter
Min.
Max.
Unit
Notes
V
IN(dc)
DC input signal voltage
–0.3
V
DDQ + 0.3
—
1)
V
IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
V
ID(dc)
DC differential input voltage
0.25
V
DDQ + 0.6
—
2)
V
ID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc).
V
ID(ac)
AC differential input voltage
0.5
V
DDQ + 0.6
V
3)
V
ID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac).
V
IX(ac)
AC differential cross point input voltage
0.5
× V
DDQ – 0.175
0.5
× V
DDQ + 0.175
V
4)
4) The value of
V
IX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
V
OX(ac)
AC differential cross point output voltage 0.5
× V
DDQ – 0.125
0.5
× V
DDQ + 0.125
V
5)
5) The value of
V
OX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
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