參數(shù)資料
型號: HYB18T1G800C4F-3
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, 0.45 ns, PBGA60
封裝: GREEN, PLASTIC, TFBGA-60
文件頁數(shù): 13/58頁
文件大?。?/td> 1898K
代理商: HYB18T1G800C4F-3
HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
20
04212008-66HT-ZLFE
3.2
Extended Mode Register EMR(1)
The Extended Mode Register EMR(1) stores the data for
enabling or disabling the DLL, output driver strength, additive
latency, OCD program, ODT, DQS and output buffers
disable, RDQS and RDQS enable.
TABLE 11
Extended Mode Register Definition, BA2:0 = 001B
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address 2
0B
BA2 Bank Address
BA1
15
Bank Address 1
0B
BA1 Bank Address
BA0
14
Bank Address 0
1B
BA0 Bank Address
A13
13
w
Address Bus
0B
A13 Address bit 13
Qoff
12
w
Output Disable
0B
QOff Output buffers enabled
1B
QOff Output buffers disabled
RDQS
11
w
Read Data Strobe Output (RDQS, RDQS)
0B
RDQS Disable
1B
RDQS Enable
DQS
10
w
Complement Data Strobe (DQS Output)
0B
DQS Enable
1B
DQS Disable
OCD
Program
[9:7]
w
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
[5:3]
w
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
110B AL 6
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