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參數(shù)資料
| 型號： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 18/58頁 |
| 文件大小： | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
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HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
25
04212008-66HT-ZLFE
4
Truth Tables
The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two
SDRAM.
TABLE 15
Command Truth Table
Function
CKE
CS RAS
CAS WE BA0
BA1
BA2
A[13:11] A10 A[9:0]
Note1)2)3)
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means H or L (but a defined logic level).
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
Previous
Cycle
Current
Cycle
(Extended) Mode Register Set H
H
L
BA
OP Code
4)5)6)
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS and CKE at the rising edge of the clock.
5) Bank addresses BA[2:0] determine which bank is to be operated upon. For (E)MRS BA[2:0] selects an (Extended) Mode Register.
6) All banks must be in a precharged idle state, CKE must be high at least for
t
XP and all read/write bursts must be finished before the
(Extended) Mode Register set Command is issued.
Auto-Refresh
H
L
H
X
Self-Refresh Entry
H
L
H
X
7)
V
REF must be maintained during Self Refresh operation.
Self-Refresh Exit
L
H
X
8) Self Refresh Exit is asynchronous.
LH
H
Single Bank Precharge
H
L
H
L
BA
X
L
X
Precharge all Banks
H
L
H
L
X
H
X
Bank Activate
H
L
H
BA
Row Address
Write
H
L
H
L
BA
Column
L
Column
9) Burst reads or writes at BL = 4 cannot be terminated. See Chapter 3.5 for details.
Write with Auto-Precharge
H
L
H
L
BA
Column
H
Column
Read
H
L
H
L
H
BA
Column
L
Column 4)5)9)
Read with Auto-Precharge
H
L
H
L
H
BA
Column
H
Column
No Operation
H
X
L
H
X
Device Deselect
H
X
H
X
Power Down Entry
H
L
H
X
10) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements.
LH
H
Power Down Exit
L
H
X
LH
H
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| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
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