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參數(shù)資料
| 型號(hào)： | HX6218DBNC |
| 元件分類： | FIFO |
| 英文描述： | 2K X 18 OTHER FIFO, 30 ns, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 717K |
| 代理商： | HX6218DBNC |
FIFO – HX6409/HX6218/HX6136
www.honeywell.com
3
SIGNAL DEFINITIONS
Signal Name
I/O
Description
D: 0 – 35
I
Data Inputs: Data Inputs are written into the FIFO on the rising edge of CKW when
ENW is active and the FIFO is not full.
Q: 0 – 35
O
Data Outputs: Data Outputs are read out of the FIFO memory and updated on the
rising edge of CKR when ENR is active and the FIFO is not Empty. The Data Outputs
are in a high impedance state if OE is not active.
ENW
I
Enable Write: An active low signal that enables the write of the Data Inputs on the
CKW rising edge (if FIFO is not full).
ENR
I
Enable Read: An active low signal that enables the read and update of the Data
Outputs on the CKR rising edge (if FIFO is not empty).
CKW
I
Write Clock: The rising edge clocks data into the FIFO when ENW is low (active). On
the rising edge, this signal also updates the Half Full, Full, Full, and Full Fault Flags.
CKR
I
Read Clock: The rising edge clocks data out of the FIFO when ENR is low (active). On
the rising edge, this signal also updates the Full, Empty, and Empty Fault Flags.
HF
O
Half Full Flag: Updated on the rising edge of CKW and indicating that the FIFO is
greater than half full.
E / F
O
Empty or Full Flag: Empty is updated on the rising edge of CKR, and Full is updated
on the rising edge of CKW.
QF/TQF
O
Full or Full Flag: Full is updated on the rising edge of CKR, and Full is
updated on the rising edge of CKW. Full signifies 256 or less words in the 1K x 36
FIFO and Full signifies 256 words or less until a full condition.
EF_Fault
O
Empty or Full Fault Flag: empty Fault is updated on the rising edge of CKR, and Full
Fault is updated on the rising edge of CKW. Empty Fault signifies a read to an already
empty FIFO, and Full Fault signifies a write to an already full FIFO. Once a fault
condition is detected, the Fault Flag remains latched until the empty or full condition is
removed.
MR
I
Master Reset: Active low signal which, when active, resets device to empty condition
OE
I
Output Enable: Active low signal which, when active, enables low impedance Data
Outputs, Q: 0 – 35
D2
D1
D0
Conditions
O
X
Parity Disabled
I
O
Generate Even Parity, Q8, Q17, Q26, Q35
I
O
I
Generate Odd Parity, Q8, Q17, Q26, Q35
I
O
Check for Even Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal
I
Check for Odd Parity, Error on Q8, Q17, Q35, Error is a Low Signal
PROGRAMMABLE PARITY OPTIONS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HX6228TBNC | 128K X 8 STANDARD SRAM, 25 ns, CDFP32 |
| HX6228TQHC | 128K X 8 STANDARD SRAM, 25 ns, CDFP32 |
| HX6228ASNT | 128K X 8 STANDARD SRAM, 25 ns, CDFP40 |
| HX6409TQHT | 4K X 9 OTHER FIFO, 30 ns, CDFP32 |
| HX80ML | 0.02 A, 8000 V, SILICON, SIGNAL DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HX6218DBNT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBRC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBRT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DENC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DENT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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