參數(shù)資料
型號(hào)： HSP50214B
廠商： Intersil Corporation
英文描述： Programmable Downconverter
中文描述： 可編程變頻器
文件頁(yè)數(shù)： 15/60頁(yè)
文件大?。?/td> 573K
代理商： HSP50214B
3-15
The phase of the Carrier NCO can be shifted by adding a
10-bit phase offset to the MSB’s (modulo 360o) of the output
of the phase accumulator. This phase offset control has a
resolution of 0.35oand can be interpreted as two’s
complement from -180oto 180o
(
-
π
to
π
)
or as binary from 0
to 360o
(
0 to 2
π
)
. The phase offset is given by:
PO 2
10
(
)
×
(
)
≤
–
(
;
=
512 to 511
–
(
)
or, in terms of the parameter to be programmed:
where PO is the 10-bit two’s complement value loaded into the
Phase Offset Register (Control Word 4, Bits 9-0). For example,
a value of 32 (decimal) loaded into the Phase Offset Register
would produce a phase offset of 11.25
o
and a value of -512
would produce an offset of 180
o
. The phase offset is loaded via
the microprocessor interface. See the Microprocessor Write
Section on instructions for writing Control Word 4.
The most significant 18 bits from the phase adder are used
as the address a sin/cos lookup table. This lookup table
maps phase into sinusoidal amplitude. The sine and cosine
values have 18 bits of amplitude resolution. The spurious
components in the sine/cosine generation are at least
-102dBc. The sine and cosine samples are routed to the
mixer section where they are multiplied with the input
samples to translate the signal of interest to baseband.
The mixer multiplies the 14-bit input by the 18-bit quadrature
sinusoids. The mixer equations are:
The mixer output is rounded symmetrically to 15 bits.
To allow the frequency and phase of multiple parts to be
updated synchronously, two sets of registers are used for
latching the center frequency and phase offset words. The
offset phase and center frequency Control Words are first
loaded into holding registers. The contents of the holding
registers are transferred to active registers in one of two ways.
The first technique involves writing to a specific Control Word
Address. A processor write to Control Word 5, transfers the
center frequency value to the active register while a processor
write to Control Word 6 transfers the phase offset value to the
active register.
The second technique, designed for synchronizing updates to
multiple parts, uses the SYNCIN1 pin to update the active
registers.WhenControlWord1,Bit20issetto1,theSYNCIN1
pincausesboththecenterfrequencyandPhaseOffsetHolding
Registers to be transferred to active registers. Additionally,
when Control Word 0, Bit 0 is set to 1, the feedback in the
phase accumulator is zeroed when the transfer from the
holding to active register occurs. This feature provides
synchronization of the phase accumulator starting phase of
multiple parts. It can also be used to reset the phase of the
NCO synchronous with a specific event.
The carrier offset frequency is loaded using the COF and
COFSYNC pins. Figure 13 details the timing relationship
between COF, COFSYNC and CLKIN. The offset frequency
word can be zeroed if it is not needed. Similarly, the
Sample Offset Frequency Register controlling the Re-
Sampler NCO is loaded via the SOF and SOFSYNC pins.
The procedure for loading data through the two pin NCO
interfaces is identical except that the timing of SOF and
SOFSYNC is relative to PROCCLK.
Each serial word has a programmable word width of either 8,
16, 24, or 32 bits (See Control Word 0, Bits 4 and 5, for the
Carrier NCO programming and Control Word 11, Bits 3 and
4, for Timing NCO programming). On the rising edge of the
clock, data on COF or SOF is clocked into an input shift
register. The beginning of a serial word is designated by
asserting either COFSYNC or SOFSYNC “high” one CLK
period prior to the first data bit.
NOTE: Serial Data must be loaded MSB first, and COFSYNC or
SOFSYNC should not be asserted for more than one
CLK cycle.
φ
OFF
2
π
2
9
PO
2
9
1
–
(
)
≤
)
(EQ. 4)
PO
INT 2
10
φ
OFF
)
2
π
]
HEX
π
–
φ
OFF
π
<
<
(
)
;
=
(EQ. 4A)
I
OUT
I
IN
ω
c
(
)
cos
×
=
(EQ. 5)
Q
OUT
I
IN
ω
c
(
)
sin
×
=
(EQ. 5A)
COF/
SOF
MSB
MSB
CLKIN
COFSYNC/
SOFSYNC
LSB
OTE:
Data must be loaded MSB first.
IGURE 13. SERIAL INPUT TIMING FOR COF AND SOF INPUTS
Serial word width can be: 8, 16, 24, 32 bits wide.
T
D
is determined by the COFSYNC, COFSYNC rate.
FIGURE 14. HOLDING REGISTERS LOAD SEQUENCE FOR
COF AND SOF SERIAL OFFSET FREQUENCY
DATA
32
30
28
26
24
22
20
18
16
14
12
10
8
54
50
46
42
38
T
D
T
D
T
D
T
D
34
30
26
22
18
14
10
6
2
6
4
2
0
S
DATA TRANSFERRED
TO HOLDING REGISTER
CLK TIMES
ASSERTION OF
COFSYNC, SOFSYNC
(8)
(32)
(16)
(24)
HSP50214B
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP50214B_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
HSP50214BVC 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214BVCZ 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214BVI 功能描述:上下轉(zhuǎn)換器 120L MQFP INDTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214BVIZ 功能描述:上下轉(zhuǎn)換器 120L MQFP INDTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
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