- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371898 > HSP50016-EV (Intersil Corporation) DDC Evaluation Platform PDF資料下載
參數(shù)資料
| 型號： | HSP50016-EV |
| 廠商： | Intersil Corporation |
| 英文描述： | DDC Evaluation Platform |
| 中文描述： | DDC的評估平臺 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大?。?/td> | 209K |
| 代理商： | HSP50016-EV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
3-205
In Up/down Chirp Mode, the phase accumulator is set to the
phase offset value and the minimum phase increment is
loaded into the Phase Increment Register. The delta phase
increment is added to the 24 LSBs of the Phase Increment
Register to form a new phase increment at each clock. The
phase increment is allowed to grow until it nears the
maximum phase increment value (as defined in the up chirp
description). The delta phase increment value is then
subtracted from the least significant bits of the Phase
Increment Register to form a new phase increment at each
clock. The phase increment is allowed to diminish until it
reaches the minimum phase increment value (as defined in
the down chirp description). The Phase Increment Register
is then reloaded with the minimum phase increment, and the
up/down cycle begins again. See Figure 6 for a graphical
representation of this process.
The minimum and maximum phase increments have
allowable values from 0 to 2
32
-1. This corresponds to the
phase increment:
FIGURE 5A. PHASE WORD DURING DOWN CHIRP
FIGURE 5B. DOWN CHIRP
FIGURE 6. UP/DOWN CHIRP
STARTING PHASE
+90
o
±
180
o
-90
o
0
o
(0)
(2)
(1)
(4)
(5)
θ
MAX INCR
-
θ
θ
MAX INCR
θ
OFFSET
(3)
θ
MAX INCR
-2
θ
θ
MAX INCR
-3
θ
MAX INCR
-4
θ
PHASE INCREMENT
TIME
PHASE
OFFSET
PHASE WORD
TIME
TIME
MAXIMUM
MINIMUM
COSINE OUTPUT OF SIN/COS GENERATOR
PHASE INCREMENT
TIME
PHASE WORD
TIME
TIME
MAXIMUM
MINIMUM
PHASE
OFFSET
COSINE OUTPUT OF SIN/COS GENERATOR
0
Phase Increment
π
1
(
2
32
–
–
)
radians
<
<
(EQ. 4)
HSP50016
相關PDF資料 |
PDF描述 |
|---|---|
| HSP50016JC-52 | Digital Down Converter |
| HSP50016JC-75 | Digital Down Converter |
| HSP50110JC-60 | Communications Tuner Circuit |
| HSP50306SC-25 | Digital QPSK Demodulator |
| HSP50306SC-2596 | Digital QPSK Demodulator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50016GC-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50016JC-52 | 功能描述:上下轉換器 DIGITAL DOWN CONVERTER 44 PLCC, 52MHZ, COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50016JC-5296 | 制造商:Rochester Electronics LLC 功能描述:TAPE AND REEL OF HSP50016JC-52 - Bulk |
| HSP50016JC-75 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL DOWN CONVERTER 44 PLCC 75MHZ COMM - Bulk |
| HSP50016JI-52 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL DOWN CONVERTER 44 PLCC, 52MHZ, COMM,INDS - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。