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| 型號(hào)： | HSP50016-EV |
| 廠商： | Intersil Corporation |
| 英文描述： | DDC Evaluation Platform |
| 中文描述： | DDC的評(píng)估平臺(tái) |
| 文件頁(yè)數(shù)： | 23/31頁(yè) |
| 文件大小： | 209K |
| 代理商： | HSP50016-EV |
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3-220
Quadrature To Real Conversion
AftertheinputdatahasbeenprocessedbytheDDC,theoutput
can be converted into a real signal if desired. In that case, the
baseband centered quadrature signal is upcobaseband. The
real part of the upconverted signal is taken as the output. To
satisfy the Nyquist criteria, the sample rate of the resulting
signal must be at least twice the minimum sample rate of the I
and Q components of the quadrature signal. This prevents one
sideband from aliasing onto the other sideband when the real
part of the output signal is taken.
The spectrum of a quadrature signal which has been over
sampled by 2 is shown in Figure 17A. This represents the
output of the filters. As described in the previous paragraph,
the oversampling is a necessary feature of this process,
since the final signal will occupy twice the bandwidth of the
filter output. To prevent aliasing upon taking the real part of
the signal, it is necessary to perform an up conversion by f”/4,
where f” is the decimated sample frequency. (Note that f
s
is
defined as the input sampling frequency, f’ is the input
sampling frequency divided by the HDF decimation rate R,
and f” is f’ divided by the FIR decimation rate. f’’ is the FIR
output sampling rate). The up conversion function is:
For n = 0, 1, 2, 3, 4,... the output values of the local oscillator
in rectangular representation are: 1 + 0j, 0 + j, -1 + 0j, 0 - j,
1 + 0j,.... Since the real half of the complex multiplication of
the local oscillator values by the filtered signal values (the
desired output is the real part of the product) require only
trivial operations, this up conversion is done in the Formatter.
Figure 17B shows the signal spectrum after up conversion.
Figure 17C shows the spectrum of the real output signal.
Continuing with the single tone example from the previous
section, the quadrature signal output from the FIR filters is:
Multiplying w(n) by the up convert function and summing the
result is equivalent to the output sequence:
Since |e
j
π
n/2
| = 1 and |w(n)| = 1, no further magnitude
corrections are required.
The setup for this application is similar to that of the down
conversion circuit given above, except the Output Formatter
is set for Real Mode (Bit 31 in Control Word 4). This bit
configures the part for up conversion by f”/4 and summing of
the real and imaginary parts of the filter output.
TABLE 16. SAMPLE FORMAT FOR CONTROL WORD 6 -
OUTPUT
BIT
POSITION
FUNCTION
DESCRIPTION
39-37
Address
110 = Control Word 6.
36
Update
1 = Control Register Update.
35
I followed by Q
1 = I and Q Data Output on I Pin.
34-29
Time Slot
Time Slot Number = 0.
28
IQCLK Polarity
0 = Data Stable on Rising Edge
of IQCLK.
27
IQCLK Duty Cycle 1 = IQCLK Duty Cycle is 50%.
26
IQCLK Duration
1 = Active Continuously.
25-24
IQCLK Three-
State Control
01 = Enable IQCLK.
23
IQSTB Polarity
0 = IQSTB Active High.
22
IQSTB Location
0 = IQSTB Active Prior to the
Beginning of the Data Word.
21-20
IQSTB
Three-State
01 = Enable IQSTB.
19
I Polarity
0 = I Output Active High.
18-17
I Three-State
Control
01 = Enable I.
16
Q Polarity
0 = Q Output Active High.
15-14
Q Three-State
Control
00 = Disable Q.
13
Input Format
1 = Two’s complement.
12-0
IQCLK Rate
All Zeroes = CLK Used to Clock
Output Bits.
1101 1000 0000 1101 0001 0010 001X XXXX XXXX XXXX
TABLE17. SUMMARY OF CONTROL WORDS FOR THE EXAMPLE
CONTROL WORD
HEX VALUE
0
0
0
0
0
0
0
0
0
0
0
1
3
X X X X X X X X 1
2
5
0
0
0
0
0
0
0
0
0
3
7
0
0
0
0
0
0
0
0
0
4
9
0
0
0
0
0
0
0
6
E
5
B 0
0
1
F 0
0
0
0
0
6
D 8
0
D 1
2
X X X X
7
0
0
0
0
0
0
0
0
0
0
e
j2
π
nf’’/4f’’
= e
j
π
n/2
(EQ. 21)
w(n) = cos((
ω
k
-
ω
c
)n) + jsin((
ω
k
-
ω
c
)n)
= e
j(
ω
k
-
ω
c
)n
(EQ. 22)
y(n) = 1 x cos((
ω
k
-
ω
c
)n),
y(n+1) = j x jsin((
ω
k
-
ω
c
)(n+1)),
y(n+2) = -1 x cos((
ω
k
-
ω
c
)(n+2)),
y(n+3) = -j x jsin((
ω
k
-
ω
c
)(n+3)),
y(n+4) = 1 x cos((
ω
k
-
ω
c
)(n+4)),...
y = cos((
ω
k
-
ω
c
)n), -sin((
ω
k
-
ω
c
)(n+1)),
-cos((
ω
k
-
ω
c
)(n+2)), sin((
ω
k
-
ω
c
)(n+3)),
cos((
ω
k
-
ω
c
)(n+4)),...
Or:
y = RE(w(n)), - IM(w(n+1)), - RE(w(n+2)), IM(w(n+3)),
RE(w(n+4)),...
(EQ. 23)
HSP50016
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PDF描述 |
|---|---|
| HSP50016JC-52 | Digital Down Converter |
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| HSP50110JC-60 | Communications Tuner Circuit |
| HSP50306SC-25 | Digital QPSK Demodulator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50016GC-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50016JC-52 | 功能描述:上下轉(zhuǎn)換器 DIGITAL DOWN CONVERTER 44 PLCC, 52MHZ, COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50016JC-5296 | 制造商:Rochester Electronics LLC 功能描述:TAPE AND REEL OF HSP50016JC-52 - Bulk |
| HSP50016JC-75 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL DOWN CONVERTER 44 PLCC 75MHZ COMM - Bulk |
| HSP50016JI-52 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL DOWN CONVERTER 44 PLCC, 52MHZ, COMM,INDS - Bulk |
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