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參數(shù)資料
| 型號： | HSP50016-EV |
| 廠商： | Intersil Corporation |
| 英文描述： | DDC Evaluation Platform |
| 中文描述： | DDC的評估平臺 |
| 文件頁數(shù)： | 27/31頁 |
| 文件大?。?/td> | 209K |
| 代理商： | HSP50016-EV |
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3-224
Let’s return to the clock calculation example found in the Output
Formatter, and add the requirement of 4 time slots. The
calculations in the Example Clock Calculation Section remain
true, but step 8 must be added:
8. Now lets consider the multichannel timing. Each channel
must output the data at no less than 1.725MHz to get all
the I/Q data out in the allocated time for the assigned time
slot. Time margin is created when the output is clocked out
at a higher rate. Because each channel is outputting data
in only one of four channels, the effective output rate for
each channel is 1.725MHz /4 = 431.25kHz, even though
the part is outputting data 1.7MHz in every time slot.
. . . . . . . . . . Effective Channel Output Rate = 431.25kHz
Alternatively, the processor can request data from each of
the DDCs asynchronously. In this setup, Requested Output
Mode is used. The Data Concentrator polls each channel
individually and is responsible for ensuring that each
channel is polled before the output data is lost. The Data
Concentrator is a custom circuit designed by the user. A
Block Diagram of such a system is shown in Figure 23. The
interface between the controller and the DDCs has been
omitted for the sake of clarity.
References
[1] Hogenauer, Eugene V., An Economical Class of Digital
Filters for Decimation and Interpolation, IEEE
Transactions on Acoustics, Speech and Signal
Processing, April 1981.
[2] IEEE Standard Test Access Port and Boundary-Scan
Architecture, IEEE Std 1149.1 - 1990.
HSP50016
I
IQCLK
IQSTB
IQSTRT
HSP50016
I
IQCLK
IQSTB
IQSTRT
A0-15
D0
DATA0-15
CLK
DATA0-15
CLK
DATA
FROM
A/D
SYSTEM
CLOCK
DATA
R/W
STRB
CONCENTRATOR
MICRO-
PROCESSOR
FIGURE 23. CIRCUIT FOR MULTIPLE CHANNEL OPERATION
(REQUESTED OUTPUT)
HSP50016
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