- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371898 > HSP50016-EV (Intersil Corporation) DDC Evaluation Platform PDF資料下載
參數(shù)資料
| 型號： | HSP50016-EV |
| 廠商： | Intersil Corporation |
| 英文描述： | DDC Evaluation Platform |
| 中文描述： | DDC的評估平臺 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 209K |
| 代理商： | HSP50016-EV |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
3-200
Pin Description
NAME
TYPE
DESCRIPTION
V
CC
-
+5V Power.
GND
-
Ground.
DATA0-15
I
Input Data Bus. Selectable between two's complement and offset binary. DATA0 is the LSB.
CLK
I
Clock for input data bus. f
S
is the frequency of CLK, which is also the input sample rate.
RESET
I
RESET initializes the internal state of the DDC. During RESET, all internal processing stops. RESET
facilitates the synchronization of multiple chips for Auto Three-State operation. If the Force bits in Control
Word 7 are inactive and the IEEE Test Access Port is in an Idle state, RESET causes the IQCLK, IQSTB,
I and Q outputs to go to a high impedance state.
All Control Registers are updated from their respective Control Buffer Registers on the third rising edge
of CLK after the deassertion of RESET. If RESET is deasserted t
RS
nanoseconds prior to the rising edge
of CLK, the internal reset will deassert synchronously. If t
RS
is violated, then the circuit contains a syn-
chronizer which will cause reset to be deasserted internally one or more clocks later.
An initial reset is required to guarantee proper operation of the DDC. Active low.
I
O
The I output has three modes: I data; I data followed by Q data; real data.
Q
O
The Q output has two modes: Q data and the carry out of the Phase Adder.
IQCLK
O
IQ Clock: Bit or word clock for the I and Q outputs.
IQSTB
O
IQ Strobe: Beginning or end of word indicator for I and Q.
IQSTRT
I
IQ Start: Initiates output data sequence. Active low.
CDATA
I
Control Data: Port for control data input.
CCLK
I
Control Data Clock: Control data input bit clock.
CSTB
I
Control Data Strobe: Beginning of word indicator for control data.
CS
I
Chip Select: Enables control data loading of DDC. Active low.
TCK
I
Test Clock: Bit Clock for IEEE 1149.1 Data. This signal should be either tied low or pulled high when the
TAP is not used.
TMS
I
Test Port Mode Select: This signal should be either left unconnected or pulled high when the TAP is not
used.
TDI
I
Test Data Input for IEEE Test Port: This signal should be either left unconnected or pulled high when the
TAP is not used.
TDO
O
Test Data Output for IEEE Test Port: This output will be in the high impedance state when the TAP is
not used.
TRST
I
Test Port Reset. Active Low. This signal should be tied low when the TAP is not used.
HSP50016
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50016JC-52 | Digital Down Converter |
| HSP50016JC-75 | Digital Down Converter |
| HSP50110JC-60 | Communications Tuner Circuit |
| HSP50306SC-25 | Digital QPSK Demodulator |
| HSP50306SC-2596 | Digital QPSK Demodulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50016GC-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50016JC-52 | 功能描述:上下轉(zhuǎn)換器 DIGITAL DOWN CONVERTER 44 PLCC, 52MHZ, COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50016JC-5296 | 制造商:Rochester Electronics LLC 功能描述:TAPE AND REEL OF HSP50016JC-52 - Bulk |
| HSP50016JC-75 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL DOWN CONVERTER 44 PLCC 75MHZ COMM - Bulk |
| HSP50016JI-52 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL DOWN CONVERTER 44 PLCC, 52MHZ, COMM,INDS - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。