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參數(shù)資料
| 型號： | HI5731BIBZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 12BIT 100MSPS 28SOIC |
| 標準包裝： | 1 |
| 設置時間： | 20ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 650mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 100M |
| 其它名稱： | HI5731BIBZ-TDKR |
4
Spurious Free Dynamic Range to Nyquist
(Note 3)
fCLK = 40MSPS, fOUT = 2.02MHz, 20MHz Span
-
70
-
dBc
fCLK = 80MSPS, fOUT = 2.02MHz, 40MHz Span
-
70
-
dBc
fCLK = 100MSPS, fOUT = 2.02MHz, 50MHz Span
-
69
-
dBc
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, VREF
(Note 4)
-1.27
-1.23
-1.17
V
Internal Reference Voltage Drift
(Note 3)
-
175
-
V/oC
Internal Reference Output Current Sink/Source
Capability
(Note 3)
-125
-
+50
A
Internal Reference Load Regulation
IREF = 0 to IREF = -125A-
50
-
V
Input Impedance at REF OUT pin
(Note 3)
-
1.4
-
k
Amplifier Large Signal Bandwidth (0.6VP-P)
Sine Wave Input, to Slew Rate Limited (Note 3)
-
3
-
MHz
Amplifier Small Signal Bandwidth (0.1VP-P)
Sine Wave Input, to -3dB Loss (Note 3)
-
10
-
MHz
Reference Input Impedance
(Note 3)
-
12
-
k
Reference Input Multiplying Bandwidth (CTL IN)
RL = 50, 100mV Sine Wave, to -3dB Loss at IOUT
(Note 3)
-
200
-
MHz
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, VIH
(Note 4)
2.0
-
V
Input Logic Low Voltage, VIL
(Note 4)
-
0.8
V
Input Logic Current, IIH
(Note 4)
-
400
A
Input Logic Current, IIL
(Note 4)
-
700
A
Digital Input Capacitance, CIN
(Note 3)
-
3.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 1 (Note 3)
3.0
2.0
-
ns
Data Hold Time, tHLD
See Figure 1 (Note 3)
0.5
0.25
-
ns
Propagation Delay Time, tPD
See Figure 1 (Note 3)
-
4.5
-
ns
CLK Pulse Width, tPW1, tPW2
See Figure 1 (Note 3)
3.0
-
ns
POWER SUPPLY CHARACTERISTICS
IEEA
(Note 4)
-
42
50
mA
IEED
(Note 4)
-
70
85
mA
ICCD
(Note 4)
-
13
20
mA
Power Dissipation
(Note 4)
-
650
-
mW
Power Supply Rejection Ratio
VCC ±5%, VEE ±5%
-
5
-
A/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 1.28mA). Ideally the
ratio should be 16.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25oC.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
Electrical Specifications
AVEE, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal
TA = 25
oC for All Typical Values (Continued)
PARAMETER
TEST CONDITIONS
HI5731BI
TA = -40
oC TO 85oC
UNITS
MIN
TYP
MAX
HI5731
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