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參數(shù)資料
| 型號： | HI5731BIBZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/17頁 |
| 文件大小： | 0K |
| 描述： | CONV D/A 12BIT 100MSPS 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 20ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 650mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 100M |
| 其它名稱： | HI5731BIBZ-TDKR |
3
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . . -5.5V
Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DVCC to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . .
±2.5mA
Voltage from CTRL IN to AVEE . . . . . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . .
±2.5mA
Reference Input Voltage Range . . . . . . . . . . . . . . . . . .-3.7V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature
HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AVEE, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal
TA = 25
oC for All Typical Values
PARAMETER
TEST CONDITIONS
HI5731BI
TA = -40
oC TO 85oC
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
12
-
Bits
Integral Linearity Error, INL
(Note 4) (“Best Fit” Straight Line)
-
0.75
1.5
LSB
Differential Linearity Error, DNL
(Note 4)
-
0.5
1.0
LSB
Offset Error, IOS
(Note 4)
-
20
75
A
Full Scale Gain Error, FSE
(Notes 2, 4)
-
1
10
%
Full Scale Gain Drift
With Internal Reference
-
±150
-
ppm
FSR/oC
Offset Drift Coefficient
(Note 3)
-
0.05
A/oC
Full Scale Output Current, IFS
-20.48
-
mA
Output Voltage Compliance Range
(Note 3)
-1.25
-
0
V
DYNAMIC CHARACTERISTICS
Throughput Rate
(Note 3)
100
-
MSPS
Output Voltage Full Scale Step
Settling Time, tSETT, Full Scale
To
±0.5 LSB Error Band RL = 50
(Note 3)
-20-
ns
Singlet Glitch Area, GE (Peak)
RL = 50 (Note 3)
-
5
-
pV-s
Doublet Glitch Area, (Net)
-3-
pV-s
Output Slew Rate
RL = 50, DAC Operating in Latched Mode (Note 3)
-
1,000
-
V/
s
Output Rise Time
RL = 50, DAC Operating in Latched Mode (Note 3)
-
675
-
ps
Output Fall Time
RL = 50, DAC Operating in Latched Mode (Note 3)
-
470
-
ps
Spurious Free Dynamic Range within a Window
(Note 3)
fCLK = 10MSPS, fOUT = 1.23MHz, 2MHz Span
-
85
-
dBc
fCLK = 20MSPS, fOUT = 5.055MHz, 2MHz Span
-
77
-
dBc
fCLK = 40MSPS, fOUT = 16MHz, 10MHz Span
-
75
-
dBc
fCLK = 50MSPS, fOUT = 10.1MHz, 2MHz Span
-
80
-
dBc
fCLK = 80MSPS, fOUT = 5.1MHz, 2MHz Span
-
78
-
dBc
fCLK = 100MSPS, fOUT = 10.1MHz, 2MHz Span
-
79
-
dBc
HI5731
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