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參數(shù)資料
| 型號(hào)： | HB56S864ESN-7 |
| 元件分類： | DRAM |
| 英文描述： | 8M X 64 EDO DRAM MODULE, 70 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 11/34頁 |
| 文件大小： | 338K |
| 代理商： | HB56S864ESN-7 |
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HB56S872ESN Series, HB56S864ESN Series
19
14. t
WCS, tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if t
WCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥ t
RWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min) or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥
t
CPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at
access time) is indeterminate.
15. These parameters are referred to
CAS leading edge in early write cycles and to WE leading edge
in delayed write or read-modify-write cycles.
16. t
RASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t
AA, tCAC and tCPA.
18. In delayed write or read-modify-write cycles,
OE must disable output buffer prior to applying data
to the device. After
RAS is reset, if t
OEH ≥ tCWL, the DQ pin will remain open circuit (high
impedance); t
OEH < tOEH, invalid data will be out at each DQ.
19. All the V
CC and VSS pins shall be supplied with the same voltages.
20. t
HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode
RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of
CAS cycle (t
CAS + tCP + 2tT) becomes greater
than the specified t
HPC (min) value. The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
21. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC / VSS line noise, which causes to degrade VIH min./ VIL max level.
22. Data output turns off and becomes high impedance from later rising edge of
RAS and CAS. Hold
time and turn off time are specified by the timing specifications of later rising edge of
RAS and
CAS between t
OHR and tOH, and between tOFR and tOFF.
23. XXX: H or L (H: V
IH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH or VIL.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HB56S864ESN-7B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 EDO Page Mode DRAM Module |
| HB56S864ESN-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 EDO Page Mode DRAM Module |
| HB56S872ES-6B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56S872ES-7B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56S872ES-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
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