參數(shù)資料
型號(hào)： HB52F169E1
廠商： Hitachi,Ltd.
英文描述： 128 MB Registered SDRAM DIMM(128 MB 寄存同步DRAM DIMM)
中文描述： 128 MB的注冊(cè)SDRAM的內(nèi)存（128 MB的寄存同步的DRAM內(nèi)存）
文件頁(yè)數(shù)： 46/57頁(yè)
文件大?。?/td> 870K
代理商： HB52F169E1
HB52F169E1-75F
46
Others
Power-down mode:
The SDRAM module enters power-down mode when CKE goes Low in the IDLE state.
In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down
mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM module exits from
the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is
not performed.
Clock suspend mode:
By driving CKE to Low during a bank-active or read/write operation, the SDRAM
module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the
internal state is maintained. When CKE is driven High, the SDRAM module terminates clock suspend mode,
and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence:
The SDRAM module should be gone on the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes.
The CK pin is stabilized within 100
μ
s after power stabilizes before the following initialization sequence.
The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has V
CC
clamp diodes for CK, CKE, S, DQMB and DQ pins. If these pins go high
before power up, the large current flows from these pins to V
CC
through the diodes.
Initialization sequence:
When 200
μ
s or more has past after the above power-up sequence, all banks must
be precharged using the precharge command (PALL). After t
RP
delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQM, DQMU/DQML to High, the output buffer becomes High-Z during Initialization sequence, to
avoid DQ bus contention on memory system formed with a number of device.
Initialization sequence:
When 200
μ
s or more has past after the above power-up sequence, all banks must
be precharged using the precharge command (PALL). After t
RP
delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQMB to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus
contention on memory system formed with a number of device.
Stabilization time:
The PLL requires a stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required following power-up. So this SDRAM module needs dam-
my cycle for 50
μ
s after power-up.
V
CC
Power up sequence
Initialization sequence
100
μ
s
0 V
Low
Low
Low
CKE, DQMB
CK
S
, DQ
200
μ
s
Power stabilize
相關(guān)PDF資料
PDF描述
HB52F649E1 512 MB Registered SDRAM DIMM 64-Mword 】 72-bit, 133 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M 】 4 Components) PC133SDRAM
HB52F649E1-75B 512 MB Registered SDRAM DIMM 64-Mword 】 72-bit, 133 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M 】 4 Components) PC133SDRAM
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HB52F88EM 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
HB52F168EN 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
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