參數(shù)資料
型號(hào)： GT-64010A
廠商： Galileo Technology Services, LLC
英文描述： System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器）
文件頁(yè)數(shù)： 57/111頁(yè)
文件大?。?/td> 671K
代理商： GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
5
Rev is io n 1. 1
Galileo
TechnologyTM
3.2.
Pin Assignment Table
Pin Name
Type
Description
CPU Interface
Release*
I
Release Interface: Signals to the GT-64010A that the processor is
releasing the system interface to slave state.
WrRdy*
O
Write Ready: The GT-64010A signals that it can accept a proces-
sor write request.
ValidIn*
O
Valid Input: The GT-64010A signals that it is driving valid data on
the SysAD bus, and a valid data identifier on the SysCmd bus.
ValidOut*
I
Valid Output: Signals that the processor is driving valid address or
data on the SysAD bus and a valid command or data identifier on
the SysCmd bus.
SysAD[63:0]
I/O
System Address/Data Bus: A 64-bit address and data bus for
communication between the processor and GT-64010A.
SysCmd[8:0]
I/O
System Command/Data Identifier Bus: A 9-bit bus for command
and data identifier transmission between the processor and GT-
64010A.
Interrupt*
I/O
Interrupt: An “OR” of all the internal interrupt sources on the GT-
64010A. This pin is also sampled as an input at reset for configura-
tion purposes.
TClk
I
Clock: The input clock to the GT-64010A (up to 50MHz).
PCI Interface
PClk
I
PCI Clock: It provides the timing for the PCI-related bus transac-
tion. The PCI clock range is between 0 and 33MHz.
Rst*
I
Reset: Resets the GT-64010A to its initial state. This signal must be
asserted for at least 10 PCI clock cycles. When in the reset state, all
PCI output pins are put into tristate and all open drain signals are
floated.
PAD[31:0]
I/O
Address/Data: 32-bit multiplexed PCI address and data lines. Dur-
ing the first clock of the transaction, PAD[31:0] contains a physical
byte address (32 bits). During subsequent clock cycles, PAD[31:0]
contains data.
CBE[3:0]*
I/O
Bus Command/Byte Enable: These are multiplexed on the same
PCI pins. During the address phase of the transaction, CBE[3:0]*
provide the bus command. During the data phase, these lines pro-
vide the byte enable. Byte enable determines which bytes carry
valid data.
Par
I/O
Parity: Calculated by the GT-64010A as an even parity bit for the
PAD[31:0] and CBE[3:0]* lines.
Frame*
I/O
Frame: It is asserted by the GT-64010A to indicate the beginning
and duration of a master transaction. Frame* asserts to indicate the
beginning of the cycle. While Frame* is asserted, data transfer con-
tinues. Frame* deasserts to indicate that the next data phase is the
final data phase transaction. Frame* is monitored by the GT-
64010A when it acts as a target.
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