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參數(shù)資料
| 型號： | GT-64010A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器） |
| 文件頁數(shù)： | 13/111頁 |
| 文件大?。?/td> | 671K |
| 代理商： | GT-64010A |
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GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
11
Rev is io n 1. 1
Galileo
TechnologyTM
signals can be shaped by specifying the following: the number of cycles from the assertion of ADS* to the first assertion
of write, the number of cycles the write pulse is active (LOW) - could be extended by Ready*, and the number of cycles
the write signal is non-active between consecutive writes. The timing parameters of the write signals determine the
length of active CS* (or DMAAck*) signals, as well as the external latch control and burst address change timing.
For read cycles, a device access time to first data (could be extended by Ready*) and to the following data (could be
extended by Ready*) in burst accesses defines the cycle parameters. The access time determines the timing that data
will be latched, and when the burst address will change.
The device controller supports up to 8 word burst accesses. The burst address is supported by a three bit wide address
bus (BAdr[2:0]) that is different from the multiplexed AD bus. The same bus also supports the packing of data into a 64-
bit double word, in reads from devices that are 8-bits to 32-bits wide. Devices that are 8-bits or 16-bits wide only are
supported by partial reads (up to 64-bits). The controller supports CPU writes of 1 to 8 bytes to 8-bit or 16-bit wide
devices. It supports DMA/PCI writes of 1 to 4 bytes to 8-bit or 16-bit wide devices.
4.7.1. Ready* Support
The Ready* pin is sampled on two different occasions: on the last rising edge of the WrActive phase during a write
cycle and one clock before the data is sampled to the GT-64010A during both AccToFirst and AccToNext phases. Dur-
ing all other phases Ready* is not sampled by the GT64010A.
If Ready* is not asserted during these clocks, the WrActive, AccToFirst or AccToNext phases are extended until Ready*
is asserted again. See the timing diagrams added for read and write cycles that are controlled by Ready*
4.8
DMA Controller
The DMA controller can move data between devices on the AD bus, between devices on the PCI bus, or between
devices on the AD bus and devices on the PCI bus. All DMA transfers use an internal 32-byte FIFO for moving data.
Data is transferred from the source device into the internal FIFO, and from the internal FIFO to the destination device.
The length of each transfer of DMA can be limited to 1, 2, 4, 8, 16 or 32 bytes. Accesses can be non-aligned both in the
source and the destination. The DMA can be programmed to move up to 64 KBytes of data in each transaction.
The DMA controller supports chained and non-chained modes of operation. In the non-chained mode the CPU or the
PCI program the DMA channel for each DMA transaction. In chained mode, the DMA controller programs itself for the
next DMA operation by fetching the information from a linked list of records in memory.
The DMA controller can be programmed to assert an interrupt in chained mode at the end of every DMA transaction, or
when the Next Pointer Register is Null and Byte Count reaches terminal count. In non-chained mode, the DMA will
assert an interrupt every time the Byte Count reaches terminal count.
DMA accesses can be initiated by an external request by asserting one of the four DMAReq[3:0]* pins (Demand
mode), or by setting an internal bit in a register (Block mode).
Accesses by the four DMA channels can be prioritized via a programmable arbiter. Channels 0 and 1 are in one group
and channels 2 and 3 are in another group. Inside each group, the priority can be fixed so a selected channel number
can have a higher priority, or both can have the same priority in round-robin fashion. The same scheme applies
between the two groups, they can have fixed or round-robin priority.
4.9
PCI Bus
The GT-64010A interfaces directly with the PCI bus. As a PCI device, the GT-64010A can be either a master initiating
a PCI bus operation or a target responding to a PCI bus operation. When the CPU or the internal DMA machine ini-
tiates a bus cycle to a PCI device, the GT-64010A becomes a PCI bus master and translates the CPU cycle into the
appropriate PCI bus cycle. The cycles are:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64010A-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64010AB1 | 制造商:GALILEO 功能描述:* |
| GT64010A-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64011-A1-PBB-C000 | 制造商:Marvell 功能描述: |
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
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