參數(shù)資料
型號： GT-64010A
廠商： Galileo Technology Services, LLC
英文描述： System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器）
文件頁數(shù)： 38/111頁
文件大小： 671K
代理商： GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
32
R e v i s ion 1 . 1
Galileo
TechnologyTM
C h an n e l 2 DM A D est i n a t i o n A d d r ess, O f f s e t : 0 x828
C h an n e l 3 DM A D est i n a t i o n A d d r ess, O f f s e t : 0 x82c
C h an n e l 0 Ne x t R eco rd P o i n t e r, O f f set : 0x8 30
C h an n e l 1 Ne x t R eco rd P o i n t e r, O f f set : 0x8 34
C h an n e l 2 Ne x t R eco rd P o i n t e r, O f f set : 0x8 38
C h an n e l 3 Ne x t R eco rd P o i n t e r, O f f set : 0x8 3c
5.9
DMA Channel Control
Each DMA channel has a control register to set its mode of operation independently of the other three channels. A
channel can be programmed to transfer data through the GT-64010A. The DMA reads data from the source address
(PCI, Devices or DRAM) into an internal 32-byte FIFO. From the internal FIFO, the data is written to a destination
address (PCI as master, Devices or DRAM) that can be independent from the source address.
Source addresses and destination addresses can be programmed to increment, decrement, or hold the same value
throughout the DMA transfer. For devices that can absorb a limited number of bytes at a time, the channel can be pro-
grammed to limit the number of bytes transferred in each DMA cycle. DMA accesses can be initiated by an external
source (Demand mode) by asserting one of the four DMAReq[3:0]* pins, or by an internal request (Block mode) until
the byte count reaches zero.
All four channels have chaining support via linked lists of records. When the chaining mode is enabled, the DMA con-
troller will fetch the information (the record) for a new DMA transfer directly out of memory (or a device or the PCI) with-
Bits
Field Name
Function
Initial Value
31:0
DestAdd
The address that the DMA controller will write the data
to.
0x0
Bits
Field Name
Function
Initial Value
31:0
DestAdd
The address that the DMA controller will write the data
to.
0x0
Bits
Field Name
Function
Initial Value
31:0
NextRecPtr
The address for the next record of DMA. A value of 0
means a NULL pointer (end of the chained list).
0x0
Bits
Field Name
Function
Initial Value
31:0
NextRecPtr
The address for the next record of DMA. A value of 0
means a NULL pointer (end of the chained list).
0x0
Bits
Field Name
Function
Initial Value
31:0
NextRecPtr
The address for the next record of DMA. A value of 0
means a NULL pointer (end of the chained list).
0x0
Bits
Field Name
Function
Initial Value
31:0
NextRecPtr
The address for the next record of DMA. A value of 0
means a NULL pointer (end of the chained list).
0x0
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參數(shù)描述
GT64010A-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
GT64010AB1 制造商:GALILEO 功能描述:*
GT64010A-P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
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