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參數(shù)資料
| 型號(hào)： | GT-64010A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器） |
| 文件頁數(shù)： | 24/111頁 |
| 文件大?。?/td> | 671K |
| 代理商： | GT-64010A |
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GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
2
R e v i s ion 1 . 1
Galileo
TechnologyTM
1. OVERVIEW
The GT-64010A is a highly integrated system controller that supports middle to high performance embedded control
applications with state-of-the-art 64-bit MIPS processors, while significantly reducing their cost, complexity, device
count, and board space.
The architecture of the chip supports several optional system architectures for different applications and cost/perfor-
mance points. It is possible to design a powerful system with minimal glue logic, or add commodity logic (controlled by
the GT-64010A) for differentiated system architectures that attain higher performance.
The GT-64010A has a three bus architecture:
a)
64-bit interface to the CPU,
b)
32-bit interface to the memory subsystem, with a bypassing option to create a 64-bit path to the CPU,
c)
32-bit interface to the PCI bus.
The three buses are de-coupled from each other in most accesses, enabling concurrent operation of the CPU, PCI
devices, and accesses to memory. For example, the CPU can write to the on-chip write buffer, a DMA agent can move
data from DRAM to its own buffers, and a PCI device can write into an on-chip FIFO at the same time.
1.1
Processor Interface
The GT-64010A supports without glue logic the IDT/MIPS family of R4xxx and R5000 Orion processors. It supports
bus frequencies of up to 50MHz, while the processor can operate internally at 80 to 200MHz. The GT-64010A has a
deep write buffer with the ability to absorb several write transactions from the CPU. For systems that want to increase
performance even more, the GT-64010A supports the Galileo GT-64012 secondary cache controller. Systems with
CPUs that run internally at 3x or more of the external frequency can particularly benefit from this option.
1.2
DRAM and Device Interface
The GT-64010A has a flexible DRAM controller. It supports EDO (Hyperpage) as well as standard page mode DRAMs.
With 60ns standard DRAMs, the GT-64010A can return data at 7-2-2-2 to the CPU (four wait states to the first access).
The DRAM controller supports different depth devices in each bank for base configuration at manufacturing, and allow-
ing for field upgrades by end users. It supports 32-bit wide DRAMs for high granularity in applications where small
memory size is desirable, or 64-bit wide DRAM where higher memory performance is needed.
The GT-64010A memory controller supports different types of memory and I/O devices. It has the control signals and
the timing programmability to support devices like Flash, EPROMs, SRAMs, FIFOs, and I/O controllers, from 8-bit to
64-bit width.
Parity generation and checking is supported externally and is optional for each bank of DRAM or any other device on
the memory bus.
1.3
PCI Interface
The GT-64010A interfaces directly with the PCI bus. It can be either a master initiating a PCI bus operation or a target
responding to a PCI bus operation.
The GT-64010A incorporates 96-bytes of posted write and read prefetch buffers for efficient data transfer between the
CPU/DMA to PCI and PCI to main memory.
The GT-64010A becomes a PCI bus master when the CPU or the internal DMA engine initiates a bus cycle to a PCI
device. It translates the CPU cycle into the appropriate PCI bus cycle. These cycles can be either Memory, Interrupt
Acknowledge, Special, I/O, or Configuration cycles.
The GT-64010A acts as a target when a PCI device initiates a memory access (or an I/O access in the case of internal
registers). It responds to all memory read/write accesses, as well as to all configuration and I/O cycles in the case of
internal registers.
The GT-64010A contains the required PCI configuration registers. All the internal registers, including the PCI configu-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64010A-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64010AB1 | 制造商:GALILEO 功能描述:* |
| GT64010A-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64011-A1-PBB-C000 | 制造商:Marvell 功能描述: |
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
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