參數(shù)資料
型號： GT-64010A
廠商： Galileo Technology Services, LLC
英文描述： System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器）
文件頁數(shù)： 29/111頁
文件大小： 671K
代理商： GT-64010A
GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
24
R e v i s ion 1 . 1
Galileo
TechnologyTM
C S [ 2 ] H i g h D eco d e A d d r ess, O f f s et : 0x434
C S [ 3 ] L o w D eco d e A d d r ess, O f f s et : 0x438
C S [ 3 ] H i g h D eco d e A d d r ess, O f f s et : 0x43c
B o o t CS L o w D eco d e A d d ress , O f f set : 0x440
B o o t CS H i g h D eco d e A d d r ess , O f f set : 0x444
A d d r ess D eco d e E r ro r, O f f set : 0x4 70
5.5
DRAM Configuration
The DRAM Configuration register specifies refresh parameters and optional usage of two of the GT-64010A pins
related to the DRAM controller. The time between refresh cycles is programmable, with the option to refresh all the
banks at the same time or in staggered fashion. The pin functionality of DRAM address bit 11 can be programmed to
be ADS* only for systems that do not have deep DRAMs. This pin can also be programmed to be ADS* in device
accesses, and to function as DRAM address 11 in DRAM accesses.
Bits
Field Name
Function
Initial Value
7:0
High
Device bank 2 will be accessed when the decoded
addresses are between Low and High.
0xdf
Bits
Field Name
Function
Initial Value
7:0
Low
Device bank 3 will be accessed when the decoded
addresses are between Low and High.
0xf0
Bits
Field Name
Function
Initial Value
7:0
High
Device bank 3 will be accessed when the decoded
addresses are between Low and High.
0xfb
Bits
Field Name
Function
Initial Value
7:0
Low
Boot bank will be accessed when the decoded
addresses are between Low and High.
0xfc
Bits
Field Name
Function
Initial Value
7:0
High
Boot bank will be accessed when the decoded
addresses are between Low and High.
0xff
Bits
Field Name
Function
Initial Value
31:0
ErrAddr
The addresses of accesses to invalid address ranges
(those not in the range programmed in the DRAM or
device decode registers) will be captured in this regis-
ter.
0xffffffff
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GT64010A-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
GT64010AB1 制造商:GALILEO 功能描述:*
GT64010A-P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
GT64011-A1-PBB-C000 制造商:Marvell 功能描述:
GT64115-A2-PBB-C000 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000
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