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參數(shù)資料
| 型號： | GT-64010A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統(tǒng)控制器） |
| 文件頁數(shù)： | 23/111頁 |
| 文件大小： | 671K |
| 代理商： | GT-64010A |
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GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
19
Rev is io n 1. 1
Galileo
TechnologyTM
C P U I n t e r f ac e C o n f i g u ra t i o n , O f f set : 0x000
5.3
Processor Address Space
The Decode Address registers determine which physical device group will be accessed when the CPU issues an
address. The decode to the specific bank (RAS or CAS) in each group is done in the memory control unit. The address
decoding is done by comparing bits 35:28 of the address to bits 14:7 of the Low field of all the Low Decode registers to
find a match, and by comparing address bits 27:21 to be greater than or equal to bits 6:0 of the Low fields, and less
than or equal to the High field. When an address is out of range (of all the Decode Address registers), the CPU will be
interrupted during a write access and a bus error will be asserted during a read access. The invalid address will be cap-
tured in the Bus Error Address Low and High registers. The DMA controller uses the Processor’s address decoding,
with the exception of bits 35:32.
R A S [ 1 : 0 ] L o w De c o d e Ad d r ess, O f f set : 0x 008
R A S [ 1 : 0 ] Hi g h De c o d e Ad d r ess, O f f set : 0x 010
Bits
Field name
Function
Initial Value
8:0
CacheOpMap
Cache operation mapping. Indicates which address
bits will be used for cache flush and cache invalidate
operation by the GT-64012. Bits 8:0 correspond to
SysAd[35:27].
0x0
9
CachePres
Secondary cache support.
0 - GT-64012 not present
1 - GT-64012 present
0x0
10
Reserved
Must be ‘0’.
0x0
11
WriteMod
Write mode.
0 - Pipelined writes mode
1 - R4XXX mode (2 dead-cycles minimum between
consecutive address-phases)
0x0
12
Endianess
Byte Orientation.
0 - Big Endian
1 - Little Endian
Sampled at reset via
the Interrupt* pin
Bits
Field Name
Function
Initial Value
14:0
Low
DRAM banks 1 and 0 will be accessed when the
decoded addresses are between Low and High.
0x0000
Bits
Field Name
Function
Initial Value
6:0
High
DRAM banks 1 and 0 will be accessed when the
decoded addresses are between Low and High.
0x07
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64010A-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64010AB1 | 制造商:GALILEO 功能描述:* |
| GT64010A-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64011-A1-PBB-C000 | 制造商:Marvell 功能描述: |
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
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