參數(shù)資料
型號(hào)： GS816236
廠商： GSI TECHNOLOGY
英文描述： 16Mb（512K x 36Bit）S/DCD Sync Burst SRAM(16M位（512K x 36位）可選單/雙循環(huán)取消同步?jīng)_靜態(tài)RAM(帶2位脈沖地址計(jì)數(shù)器))
中文描述： 16Mb的（為512k × 36Bit）的S /雙氰胺同步突發(fā)靜態(tài)存儲(chǔ)器（1,600位（為512k × 36位）可選單/雙循環(huán)取消同步?jīng)_靜態(tài)隨機(jī)存儲(chǔ)器（帶2位脈沖地址計(jì)數(shù)器））
文件頁(yè)數(shù)： 9/38頁(yè)
文件大?。?/td> 826K
代理商： GS816236
Rev: 2.10 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
9/38
1999, Giga Semiconductor, Inc.
Preliminary
GS816218/36/72B-225/200/180/166/150/133
Mode Pin Functions
Note:
There are pull-up devices on the ZQ, SCD DP, and FT pins and pull-down devices on the PE and ZZ pins, so those input pins can
be unconnected and the chip will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
Check for Odd Parity
Check for Even Parity
Activate 9th I/O’s (x18/36 Mode)
Deactivate 9th I/O’s (x16/32 Mode)
High Drive (Low Impedance)
Low Drive (High Impedance)
Output Register Control
FT
H or NC
L or NC
Power Down Control
ZZ
H
Single / Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
L or NC
H
L
H or NC
ByteSafe Data Parity Control
DP
Parity Enable
PE
FLXDrive Output Impedance Control
ZQ
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
相關(guān)PDF資料
PDF描述
GS816272 16Mb（256K x 72Bit）S/DCD Sync Burst SRAM(16M位（256K x 72位）可選單/雙循環(huán)取消同步靜態(tài)RAM(帶2位脈沖地址計(jì)數(shù)器))
GS8162Z18BGB-200I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18BB 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18BB-150 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18BB-150I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS816236BB-150 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 512KX36 7.5NS/3.8NS 119FBGA - Trays
GS816236BB-150I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 512KX36 7.5NS/3.8NS 119FBGA - Trays
GS816236BB-150IV 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 119FPBGA - Trays
GS816236BB-150V 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 119FPBGA - Trays
GS816236BB-200 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 512KX36 6.5NS/3NS 119FBGA - Trays
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