參數(shù)資料
型號: GS816236
廠商: GSI TECHNOLOGY
英文描述: 16Mb(512K x 36Bit)S/DCD Sync Burst SRAM(16M位(512K x 36位)可選單/雙循環(huán)取消同步?jīng)_靜態(tài)RAM(帶2位脈沖地址計數(shù)器))
中文描述: 16Mb的(為512k × 36Bit)的S /雙氰胺同步突發(fā)靜態(tài)存儲器(1,600位(為512k × 36位)可選單/雙循環(huán)取消同步?jīng)_靜態(tài)隨機存儲器(帶2位脈沖地址計數(shù)器))
文件頁數(shù): 18/38頁
文件大?。?/td> 826K
代理商: GS816236
Rev: 2.10 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
18/38
1999, Giga Semiconductor, Inc.
Preliminary
GS816218/36/72B-225/200/180/166/150/133
AC Electrical Characteristics
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter
Symbol
-225
-200
-180
-166
-150
-133
Unit
Min
4.4
1.5
Max
2.5
Min
5.0
1.5
Max
3.0
Min
5.5
1.5
Max
3.2
Min
6.0
1.5
Max
3.4
Min
6.7
1.5
Max
3.8
Min
7.5
1.5
Max
4.0
Pipeline
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
tKQX
ns
ns
ns
Clock to Output in Low-Z
tLZ
1
tKC
tKQ
tKQX
1.5
1.5
1.5
1.5
1.5
1.5
ns
Flow
Through
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
8.5
3.0
7.0
10.0
3.0
7.5
10.0
3.0
8.0
10.0
3.0
8.5
10.0
3.0
10.0
15.0
3.0
10.0
ns
ns
ns
Clock to Output in Low-Z
tLZ
1
tKH
tKL
3.0
3.0
3.0
3.0
3.0
3.0
ns
Clock HIGH Time
Clock LOW Time
1.3
1.5
1.3
1.5
1.3
1.5
1.3
1.5
1.5
1.7
1.7
2
ns
ns
Clock to Output in High-Z
tHZ
1
tOE
1.5
2.5
1.5
3.0
1.5
3.2
1.5
3.5
1.5
3.8
1.5
4.0
ns
G to Output Valid
2.5
3.2
3.2
3.5
3.8
4.0
ns
G to output in Low-Z
tOLZ
1
0
0
0
0
0
0
ns
G to output in High-Z
tOHZ
1
tS
tH
2.5
3.0
3.2
3.5
3.8
4.0
ns
Setup time
Hold time
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
ns
ns
ZZ setup time
tZZS
2
5
5
5
5
5
5
ns
ZZ hold time
tZZH
2
tZZR
1
1
1
1
1
1
ns
ZZ recovery
100
100
100
100
100
100
ns
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