參數(shù)資料
型號(hào)： GS816136CGD-250T
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 36 CACHE SRAM, 5.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁數(shù)： 13/29頁
文件大?。?/td> 797K
代理商： GS816136CGD-250T
GS816118/36CD-333/300/250
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
20/29
2004, GSI Technology
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s
applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge
of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO
pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the
various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and
TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is
placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the
RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary
Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and
the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control
of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST
instructions can be used to activate the Boundary Scan Register.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI
Test Data In
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO
Test Data Out
Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
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