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| 型號(hào)： | EVAL-ADUC7126QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 87/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7126 |
| 設(shè)計(jì)資源： | EVAL-ADUC7126 Schematic ADUC7126 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADUC7126 |
| 所含物品： | 板 |
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ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 8 of 108
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ESD TESTS
2.5 V reference, TA = 25°C
HBM Passed Up To
3
kV
FICDM Passed Up To
1.5
kV
1 All ADC channel specifications are guaranteed during normal core operation.
2 Apply to all ADC input channels.
3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4 Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 37. Based on external ADC
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7 DAC linearity is calculated using a reduced code range of 100 to 3995.
8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
9 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at 40°C, +25°C, +85°C, and +125°C.
10 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
11 Test carried out with a maximum of eight I/Os set to a low output level.
12 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
13 IOVDD power supply current increases typically by 2 mA during a Flash/EE erase cycle.
14 This current must be added to the AVDD current.
TIMING SPECIFICATIONS
I2C Timing
Table 2. I2C Timing in Fast Mode (400 kHz)
Slave
Master
Parameter
Description
Min
Max
Typ
Unit
tL
SCL low pulse width
200
1360
ns
tH
SCL high pulse width
100
1140
ns
tSHD
Start condition hold time
300
ns
tDSU
Data setup time
100
740
ns
tDHD
Data hold time
0
400
ns
tRSU
Setup time for repeated start
100
ns
tPSU
Stop condition setup time
100
800
ns
tBUF
Bus-free time between a stop condition and a start condition
1.3
μs
tR
Rise time for both SCL and SDA
300
200
ns
tF
Fall time for both SCL and SDA
300
ns
Table 3. I2C Timing in Standard Mode (100 kHz)
Slave
Parameter
Description
Min
Max
Unit
tL
SCL low pulse width
4.7
μs
tH
SCL high pulse width
4.0
ns
tSHD
Start condition hold time
4.0
μs
tDSU
Data setup time
250
ns
tDHD
Data hold time
0
3.45
μs
tRSU
Setup time for repeated start
4.7
μs
tPSU
Stop condition setup time
4.0
μs
tBUF
Bus-free time between a stop condition and a start condition
4.7
μs
tR
Rise time for both SCL and SDA
1
μs
tF
Fall time for both SCL and SDA
300
ns
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