AVDD AV
參數(shù)資料
型號： EVAL-ADUC7126QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 57/108頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7126
設計資源： EVAL-ADUC7126 Schematic
ADUC7126 Gerber Files
標準包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關產(chǎn)品： ADUC7126
所含物品： 板
ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 52 of 108
09
12
3-
0
24
AVDD
AVDD – 100mV
100mV
0x00000000
0x0FFF0000
Figure 42. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 42
becomes worse as a function of output loading. Most of the
ADuC7124/ADuC7126 data sheet specifications assume a 5 kΩ
resistive load to ground at the DAC output. As the output is
forced to source or sink more current, the nonlinear regions at
the top or bottom (respectively) of Figure 42 become larger.
With larger current demands, this can significantly limit output
voltage swing.
References to ADC and the DACs
The ADC and DACs can be configured to use the internal VREF
or an external reference as a reference source. The internal VREF
must work with an external 0.47 μF capacitor.
Table 66. Reference Source Selection for the ADC and DACs
REFCON[0]
DACxCON[1:0]
Description
0
00
ADC works with an external
reference. DACs are powered
down.
0
01
ADC works with an external
reference. DAC works with
DACREF.
0
10
Reserved.
0
11
ADC works with an external
reference. DACs work with
internal AVDD.
1
00
ADC works with an internal VREF.
DACs are powered down.
1
01
ADC works with an external
reference. DACs work with
DACREF.
1
10
ADC and DACs work with an
internal VREF.
1
11
ADC works with an internal VREF.
DACs work with an internal
AVDD.
Note that if REFCON[1] = 1, the internal VREF powers down
and the ADC cannot use the internal VREF.
Configuring DAC Buffers in Op Amp Mode
In op amp mode, the DAC output buffers are used as an op amp
with the DAC itself disabled.
If DACBCFG Bit 0 is set, ADC0 is the positive input to the op
amp, ADC1 is the negative input, and DAC0 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC0CON.
If DACBCFG Bit 1 is set, ADC2 is the positive input to the op
amp, ADC3 is the negative input, and DAC1 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC1CON.
If DACBCFG Bit 2 is set, ADC4 is the positive input to the op
amp, ADC5 is the negative input, and DAC2 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC2CON.
If DACBCFG Bit 3 is set, ADC8 is the positive input to the op
amp, ADC9 is the negative input, and DAC3 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC3CON.
DACBCFG Register
Name:
DACBCFG
Address:
0xFFFF0654
Default Value:
0x00
Access:
Read/write
Table 67. DACBCFG MMR Bit Descriptions
Bit
Description
[7:4]
Reserved. Always set to 0.
3
Set this bit to 1 to configure the DAC3 output
buffer in op amp mode.
Clear this bit for the DAC buffer to operate as
normal.
2
Set this bit to 1 to configure the DAC2 output
buffer in op amp mode.
Clear this bit for the DAC buffer to operate as
normal.
1
Set this bit to 1 to configure the DAC1 output
buffer in op amp mode.
Clear this bit for the DAC buffer to operate as
normal.
0
Set this bit to 1 to configure the DAC0 output
buffer in op amp mode.
Clear this bit for the DAC buffer to operate as
normal.
The DACBCFG write sequence is as follows:
1.
Write Code 0x9A to Register DACBKEY1.
2.
Write user value to Register DACBCFG.
3.
Write Code 0x0C to Register DACBKEY2.
相關PDF資料
PDF描述
REC5-243.3SRWZ/H4/A CONV DC/DC 5W 9-36VIN 3.3VOUT
EVAL-ADUC7023QSPZ KIT DEV FOR ADUC7023 QUICK START
RPS-1K-6-250/2.0-9 HEAT SHRINK SLEEVE
ECM30DCWH CONN EDGECARD 60POS DIP .156 SLD
SC43B-3R3 INDUCTOR SMD 3.3UH 1.44A 7.96MHZ
相關代理商/技術參數(shù)
參數(shù)描述
EVAL-ADUC7128QSPZ 功能描述:KIT DEV FOR ADUC7128 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 產(chǎn)品培訓模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標準包裝:1 系列:Blackfin® 類型:DSP 適用于相關產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
EVAL-ADUC7128QSPZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC
EVAL-ADUC7129QSPZ 制造商:Analog Devices 功能描述:- Bulk
EVAL-ADUC812QS 制造商:Analog Devices 功能描述:DEVELOPMENT KIT SYSTEM
EVAL-ADUC812QSP 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*