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| 型號(hào)： | EVAL-ADUC7126QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 85/108頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7126 |
| 設(shè)計(jì)資源： | EVAL-ADUC7126 Schematic ADUC7126 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADUC7126 |
| 所含物品： | 板 |
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ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 78 of 108
PWM GENERAL OVERVIEW
The ADuC7124/ADuC7126 integrate a 6-channel PWM
interface (PWM0 to PWM5). The PWM outputs can be
configured to drive an H-bridge or can be used as standard PWM
outputs. On power-up, the PWM outputs default to H-bridge
mode. This ensures that the motor is turned off by default. In
standard PWM mode, the outputs are arranged as three pairs of
PWM pins. The user has control over the period of each pair of
outputs and over the duty cycle of each individual output.
Table 112. PWM MMRs
Name
Function
PWMCON0
PWM control.
PWM0COM0
Compare Register 0 for PWM Output 0 and
PWM Output 1.
PWM0COM1
Compare Register 1 for PWM Output 0 and
PWM Output 1.
PWM0COM2
Compare Register 2 for PWM Output 0 and
PWM Output 1.
PWM0LEN
Frequency control for PWM Output 0 and
PWM Output 1.
PWM1COM0
Compare Register 0 for PWM Output 2 and
PWM Output 3.
PWM1COM1
Compare Register 1 for PWM Output 2 and
PWM Output 3.
PWM1COM2
Compare Register 2 for PWM Output 2 and
PWM Output 3.
PWM1LEN
Frequency control for PWM Output 2 and
PWM Output 3.
PWM2COM0
Compare Register 0 for PWM Output 4 and
Output 5
PWM2COM1
Compare Register 1 for PWM Output 4 and
Output 5
PWM2COM2
Compare Register 2 for PWM Output 4 and
Output 5
PWM2LEN
Frequency control for PWM Output 4 and
PWM Output 5.
PWMCON1
PWM control register
PWMCLRI
PWM interrupt clear.
In all modes, the PWMxCOMx MMRs control the point at
which the PWM outputs change state. An example of the first pair
of PWM outputs (PWM0 and PWM1) is shown in Figure 49.
HIGH SIDE
(PWM0)
LOW SIDE
(PWM1)
PWM0COM2
PWM0COM1
PWM0COM0
PWM0LEN
0
91
23
-1
20
Figure 49. PWM Timing
The PWM clock is selectable via PWMCON with one of the
following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or
256. The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents, as shown with the
PWM0 and PWM1 waveforms in Figure 49.
The low-side waveform, PWM1, goes high when the timer
count reaches PWM0LEN, and it goes low when the timer
count reaches the value held in PWM0COM2 or when the
high-side waveform (PWM0) goes low.
The high-side waveform, PWM0, goes high when the timer
count reaches the value held in PWM0COM0, and it goes low
when the timer count reaches the value held in PWM0COM1.
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