參數(shù)資料
型號(hào)： EVAL-AD7731EB
廠商： Analog Devices, Inc.
英文描述： Low Noise, High Throughput 24-Bit Sigma-Delta ADC
中文描述： 低噪聲，高吞吐量的24位Σ-Δ模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 6/44頁
文件大?。?/td> 411K
代理商： EVAL-AD7731EB
AD7731
–6–
REV. 0
SIGMA-
DELTA
MODULATOR
AD7731
SERIAL INTERFACE
AND CONTROL LOGIC
REGISTER BANK
CLOCK
GENERATION
PROGRAMMABLE
DIGITAL
FILTER
SIGMA-DELTA A/D CONVERTER
BUFFER
PGA
AGND
AV
DD
AIN1
AIN2
AIN3/D1
AIN4/D0
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
CS
DIN
DOUT
RESET
RDY
POL
DGND
AGND
AV
DD
DV
DD
REF IN(–) REF IN(+)
MUX
AIN5
AIN6
CALIBRATION
MICROCONTROLLER
REGISTER BANK
ALL FUNCTIONS ON THE PART
AINFORMATION AND
CONVERSION RESULTS
SEE PAGE 20
CALIBRATION
MICROCONTROLLER
CALIBRATION OPTIONS
INCLUDING SELF AND
SEE PAGE 28
*SPI IS A TRADEMARK OF MOTOROLA, INC.
BUFFER AMPLIFIER
THPRESENTS A HIGH
IALLOWING SIGNIFICANT
EXTERNAL SOURCE
IMPEDANCES
SEE PAGE 23
BURNOUT CURRENTS
TWO 100nA BURNOUT
CURRENTS ALLOW THE
IF A TRANSDUCER HAS
BUOPEN-CIRCUIT
SEE PAGE 23
PROGRAMMABLE GAIN
AMPLIFIER
SEVEN UNIPOLAR AND
SEVEN +1.28V
SEE PAGE 23
DIFFERENTIAL
REFERENCE
TPART IS DIFFERENTIAL AND
VBE NOMINALLY +2.5V OR +5V.
REFERENCE DETECT CIRCUITRY
TESTS FOR OPEN OR SHORTED
REFERENCES
SEE PAGE 24
SIGMA-DELTA ADC
THE SIGMA-DELTA
AR24 BITS NO MISSING
SICHOPPED TO REMOVE
DRIFT ERRORS
SEE PAGE 24
PROGRAMMABLE
DIGITAL FILTER
OUTPUT UPDATE RATE AND
SETTLING TIME AND THAT
HAS (SEE FIGURE 3)
TM
MODE
SEE PAGE 24
STANDBY MODE
TREDUCES POWER
CONSUMPTION TO 50
m
W
SEE PAGE 32
CLOCK OSCILLATOR
CIRCUIT
PART CAN BE PROVIDED BY
AN EXTERNALLY-APPLIED
CLCRYSTAL OR CERAMIC
RESOCLOCK PINS
SEE PAGE 31
SERIAL INTERFACE
SPI*-COMPATIBLE OR DSP-
PART (APART FROM MASTER
RESET) CAN BE ACCESSED VIA
THE SERIAL INTERFACE
SEE PAGE 33
OUTPUT DRIVERS
THE AIN3 AND AIN4 INPUT
TWO OUTPUT DIGITAL PORT
PRLINES THAT CAN BE
SERIAL INTERFACE
SEE PAGE 32
ANALOG MULTIPLEXER
FIA DIFFERENTIAL MULTIPLEXER
PAIRS TO BE SWITCHED TO THE
MVIA THE SERIAL INTERFACE
SEE PAGE 23
Figure 2. Detailed Functional Block Diagram
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