參數(shù)資料
型號： EVAL-AD7731EB
廠商： Analog Devices, Inc.
英文描述： Low Noise, High Throughput 24-Bit Sigma-Delta ADC
中文描述： 低噪聲，高吞吐量的24位Σ-Δ模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 11/44頁
文件大?。?/td> 411K
代理商： EVAL-AD7731EB
AD7731
–11–
REV. 0
Output Noise (CHP = 1, SK IP = 0)
T able III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in
chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. T he numbers are generated with a mas-
ter clock frequency of 4.9152 MHz. T hese numbers are typical and generated at a differential analog input voltage of 0 V. T he out-
put update rate is selected via the SF0 to SF11 bits of the Filter Register. T able IV, meanwhile, shows the output peak-to-peak
resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in
T able IV represent the resolution for which there will be no code flicker within a six-sigma limit. T hey are not calculated based on
rms noise but on peak-to-peak noise.
T he numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in T able III will remain the same for unipolar ranges. T o calcu-
late the number for T able IV for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.
T able III. Output Noise vs. Input Range and Update Rate (CHP = 1, SKIP = 0)
T ypical Output RMS Noise in nV
Output
Data Rate Frequency
–3 dB
SF
Word
Settling T ime
Normal
Input Range
Fast Step
6
1.28 V
6
640 mV
6
320 mV
6
160 mV
6
80 mV
6
40 mV
6
20 mV
50 Hz
100 Hz
150 Hz
200 Hz
400 Hz
800 Hz
1.97 Hz
3.95 Hz
5.92 Hz
7.9 Hz
15.8 Hz
31.6 Hz
2048
1024
683
512
256
128
440 ms
220 ms
147 ms
110 ms
55 ms
27.5 ms
40 ms
20 ms
13.3 ms
10 ms
5 ms
2.5 ms
700
980
1230
1260
2000
3800
425
550
700
840
1230
2100
265
330
445
500
690
1400
170
230
270
340
430
760
120
190
210
245
335
590
85
115
140
170
215
345
55
90
100
105
160
220
T able IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1, SKIP = 0)
Peak-to-Peak Resolution in Bits
Output
Data Rate Frequency
–3 dB
SF
Word
Settling T ime
Normal
Input Range
Fast Step
6
1.28 V
6
640 mV
6
320 mV
6
160 mV
6
80 mV
6
40 mV
6
20 mV
50 Hz
100 Hz
150 Hz
200 Hz
400 Hz
800 Hz
1.97 Hz
3.95 Hz
5.92 Hz
7.9 Hz
15.8 Hz
31.6 Hz
2048
1024
683
512
256
128
440 ms
230 ms
147 ms
110 ms
55 ms
27.5 ms
40 ms
30 ms
13.3 ms
10 ms
5 ms
2.5 ms
19
19
18.5
18.5
17.5
17
19
18.5
18
18
17.5
16.5
18.5
18.5
18
17.5
17
16
18.5
18
17.5
17.5
17
16
18
17
17
17
16.5
15.5
17.5
17
16.5
16.5
16
15
17
16
16
16
15.5
15
ON-CHIP RE GIST E RS
T he AD7731 contains 12 on-chip registers that can be accessed
via the serial port of the part. T hese registers are summarized in
Figure 4 and in T able V, and described in detail in the following
sections.
RS2 RS1 RS0
REGISTER
SELECT
DECODER
STATUS REGISTER
DATA REGISTER
MODE REGISTER
FILTER REGISTER
OFFSET REGISTER (x3)
GAIN REGISTER (x3)
TEST REGISTER
COMMUNICATIONS REGISTER
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
Figure 4. Register Overview
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