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| 型號： | EVAL-AD7731EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| 中文描述： | 低噪聲，高吞吐量的24位Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 32/44頁 |
| 文件大?。?/td> | 411K |
| 代理商： | EVAL-AD7731EB |
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AD7731
–32–
REV. 0
USING T HE AD7731
Clocking and Oscillator Circuit
T he AD7731 requires a master clock input, which may be an
external CMOS compatible clock signal applied to the MCLK IN
pin with the MCLK OUT pin left unconnected. Alternatively, a
crystal or ceramic resonator of the correct frequency can be
connected between MCLK IN and MCLK OUT in which case
the clock circuit will function as an oscillator, providing the
clock source for the part. T he input sampling frequency, the
modulator sampling frequency, the –3 dB frequency, output
update rate and calibration time are all directly related to the
master clock frequency, f
CLK IN
. Reducing the master clock
frequency by a factor of 2 will halve the above frequencies and
update rate and double the calibration time.
T he crystal or ceramic resonator is connected across the MCLK
IN and MCLK OUT pins, as per Figure 15*. When using a
master clock frequency of 4.9152 MHz, C1 and C2 should both
have a value equal to 33 pF.
AD7731
CRYSTAL OR
CERAMIC
RESONATOR
C1
C2
MCLK IN
MCLK OUT
Figure 15. Crystal/Resonator Connections
T he on-chip oscillator circuit also has a start-up time associated
with it before it has attained its correct frequency and correct
voltage levels. T he typical start-up time for the circuit is 6 ms
with a DV
DD
of +5 V and 8 ms with a DV
DD
of +3 V.
T he AD7731’s master clock appears on the MCLK OUT pin of
the device. T he maximum recommended load on this pin is one
CMOS load. When using a crystal or ceramic resonator to gen-
erate the AD7731’s clock, it may be desirable to then use this
clock as the clock source for the system. In this case, it is recom-
mended that the MCLK OUT signal is buffered with a CMOS
buffer before being applied to the rest of the circuit.
System Synchronization
T he
SYNC
input allows the user to reset the modulator and
digital filter without affecting any of the setup conditions on the
part. T his allows the user to start gathering samples of the ana-
log input from a known point in time, i.e., the rising edge of
SYNC
.
If multiple AD7731s are operated from a common master clock,
they can be synchronized to update their output registers simul-
taneously. A falling edge on the
SYNC
input resets the digital
filter and analog modulator and places the AD7731 into a con-
sistent, known state. While the
SYNC
input is low, the AD7731
will be maintained in this state. On the rising edge of
SYNC
,
the modulator and filter are taken out of this reset state and on
the next clock edge the part again starts to gather input samples.
In a system using multiple AD7731s, a common signal to their
SYNC
inputs will synchronize their operation. T his would nor-
mally be done after each AD7731 has performed its own cali-
bration or has had calibration coefficients loaded to it. T he
output updates will then be synchronized with the maximum
possible difference between the output updates of the individual
AD7731s being one MCLK IN cycle.
Single-Shot Conversions
T he
SYNC
input can also be used as a start convert command
allowing the AD7731 to be operated in a conventional converter
fashion. In this mode, the rising edge of
SYNC
starts conversion
and the falling edge of
RDY
indicates when conversion is com-
plete. T he disadvantage of this scheme is that the settling time
of the filter has to be taken into account for every data register
update.
Writing 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode regis-
ter has the same effect. T his initiates a single conversion on the
AD7731 with the part returning to idle mode at the end of
conversion. Once again, the full settling time of the filter has to
elapse before the Data Register is updated.
Note, if the FAST bit is set and the part operated in single con-
version mode, the AD7731 will continue to output results until
the
STDY
bit goes to 0.
Reset Input
T he
RESET
input on the AD7731 resets all the logic, the digital
filter and the analog modulator while all on-chip registers are
reset to their default state.
RDY
is driven high and the AD7731
ignores all communications to any of its registers while the
RESET
input is low. When the
RESET
input returns high, the
AD7731 starts to process data and
RDY
will return low after
the filter has settled indicating a valid new word in the data
register. However, the AD7731 operates with its default setup
conditions after a
RESET
and it is generally necessary to set up
all registers and carry out a calibration after a
RESET
command.
T he AD7731’s on-chip oscillator circuit continues to function
even when the
RESET
input is low. T he master clock signal
continues to be available on the MCLK OUT pin. T herefore, in
applications where the system clock is provided by the AD7731’s
clock, the AD7731 produces an uninterrupted master clock
during
RESET
commands.
Standby Mode
T he
STANDBY
input on the AD7731 allows the user to place
the part in a power-down mode when it is not required to
provide conversion results. T he part can also be placed in its
standby mode by writing 0, 1, 1 to the MD2, MD1, MD0 bits
of the Mode Register. T he AD7731 retains the contents of all its
on-chip registers (including the Data Register) while in standby
mode. Data can still be read from the part in Standby Mode.
T he ST BY bit of the Status Register indicates whether the part
is in standby or normal operating mode. When the
STANDBY
pin is taken high, the part returns to operating as it had been
prior to the
STANDBY
pin going low.
T he
STANDBY
input (or 0, 1, 1 in the MD2, MD1, MD0 bits)
does not affect the digital interface. It does, however, set the
RDY
bit and pin high and also sets the
STDY
bit high. When
STANDBY
goes high again,
RDY
and
STDY
remain high until
set low by a conversion or calibration.
*T he AD7731 has a capacitance of 5 pF on MCLK IN and 13 pF on MCLK
OUT .
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