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參數(shù)資料
| 型號(hào)： | EVAL-AD7731EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| 中文描述： | 低噪聲，高吞吐量的24位Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 37/44頁 |
| 文件大?。?/td> | 411K |
| 代理商： | EVAL-AD7731EB |
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AD7731
–37–
REV. 0
MICROCOMPUT E R/MICROPROCE SSOR INT E RFACING
T he AD7731’s flexible serial interface allows for easy interface
to most microcomputers and microprocessors. T he pseudo-code
of T able X VIII and T able X IX outline typical sequences for
interfacing a microcontroller or microprocessor to the AD7731.
Figures 18, 19 and 20 show some typical interface circuits.
T he serial interface on the AD7731 has the capability of operat-
ing from just three wires and is compatible with SPI interface
protocols. T he three-wire operation makes the part ideal for
isolated systems where minimizing the number of interface lines
minimizes the number of opto-isolators required in the system.
Register lengths on the AD7731 vary from 8 to 16 to 24 bits.
T he 8-bit serial serial ports of most microcontrollers can handle
communication with these registers as either one, two or three
8-bit transfers. DSP processors and microprocessors generally
transfer 16 bits of data in a serial data operation. Some of these
processors, such as the ADSP-2105, have the facility to program
the amount of cycles in a serial transfer. T his allows the user to
tailor the number of bits in any transfer to match the register
length of the required register in the AD7731. In any case,
writing 32 bits of data to a 24-bit register is not an issue pro-
vided the final 8 bits of the word are all 1s. T his is because the
part returns to the Communications Register following a write
operation.
AD7731 to 68HC11 Interface
Figure 18 shows an interface between the AD7731 and the
68HC11 microcontroller. T he diagram shows the minimum
(three-wire) interface with
CS
on the AD7731 hard-wired low.
In this scheme, the
RDY
bit of the Status Register is monitored
to determine when the Data Register is updated. An alternative
scheme, which increases the number of interface lines to four, is
to monitor the
RDY
output line from the AD7731. T he moni-
toring of the
RDY
line can be done in two ways. First,
RDY
can
be connected to one of the 68HC11’s port bits (such as PC0)
which is configured as an input. T his port bit is then polled to
determine the status of
RDY
. T he second scheme is to use an
interrupt driven system in which case, the
RDY
output is con-
nected to the IRQ input of the 68HC11. For interfaces which
require control of the
CS
input on the AD7731, one of the port
bits of the 68HC11 (such as PC1), which is configured as an
output, can be used to drive the
CS
input.
T he 68HC11 is configured in the master mode with its CPOL
bit set to a logic zero and its CPHA bit set to a logic one. When
the 68HC11 is configured like this, its SCLK line idles low
between data transfers. T herefore, the POL input of the AD7731
should be hard-wired low. For systems where it is preferable
that the SCLK idle high, the CPOL bit of the 68HC11 should
be set to a logic 1 and the POL input of the AD7731 should be
hard-wired to a logic high.
T he AD7731 is not capable of full duplex operation. If the
AD7731 is configured for a write operation, no data appears on
the DAT A OUT lines even when the SCLK input is active.
However, when the AD7731 is configured for continuous read
operation, data presented to the part on the DAT A IN line is
monitored to determine when to exit the continuous read mode.
SYNC
RESET
AD7731
SCLK
DATA OUT
DATA IN
CS
POL
SS
SCK
MISO
MOSI
68HC11
DV
DD
DV
DD
Figure 18. AD7731 to 68HC11 Interface
AD7731 to 8051 Interface
An interface circuit between the AD7731 and the 8X C51 micro-
controller is shown in Figure 19. T he diagram shows the mini-
mum number of interface connections with
CS
on the AD7731
hard-wired low. In the case of the 8X C51 interface the mini-
mum number of interconnects is just two. In this scheme, the
RDY
bit of the Status Register is monitored to determine when
the Data Register is updated. T he alternative scheme, which
increases the number of interface lines to three, is to monitor
the
RDY
output line from the AD7731. T he monitoring of the
RDY
line can be done in two ways. First,
RDY
can be con-
nected to one of the 8X C51’s port bits (such as P1.0) which is
configured as an input. T his port bit is then polled to determine
the status of
RDY
. T he second scheme is to use an interrupt
driven system in which case, the
RDY
output is connected to
the INT 1 input of the 8X C51. For interfaces which require
control of the
CS
input on the AD7731, one of the port bits of
the 8X C51 (such as P1.1), which is configured as an output,
can be used to drive the
CS
input.
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| EVAL-AD7731EBZ | 功能描述:BOARD EVALUATION FOR AD7731 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7732EB | 制造商:Analog Devices 功能描述:2-CHANNEL, ??10 V INPUT RANGE, HIGH THROUGHPUT, 24-BIT ADC |
| EVAL-AD7732EBZ | 功能描述:BOARD EVAL FOR AD7732 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7734EBZ | 功能描述:BOARD EVALUATION FOR AD7734 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7738EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD7738 ADC 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
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