參數(shù)資料
型號(hào)： EVAL-AD5383EB
廠商： Analog Devices, Inc.
英文描述： 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
中文描述： 32通道，3伏/ 5 V，單電源，12位，電壓輸出DAC
文件頁(yè)數(shù)： 7/40頁(yè)
文件大?。?/td> 1201K
代理商： EVAL-AD5383EB
AD5383
Parameter
LOGIC OUTPUTS (BUSY, SDO)
3
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
LOGIC OUTPUT (SDA)
3
V
OL
, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AV
DD
DV
DD
Power Supply Sensitivity
3
Midscale/ΑV
DD
AI
DD
DI
DD
AI
DD
(Power-Down)
DI
DD
(Power-Down)
Power Dissipation
Rev. 0 | Page 7 of 40
AD5383-3
1
0.4
DV
DD
– 0.5
±1
5
0.4
0.6
±1
8
2.7/3.6
2.7/5.5
–85
0.375
0.475
1
2
20
39
Unit
V max
V min
μA max
pF typ
V max
V max
μA max
pF typ
V min/max
V min/max
dB typ
mA/channel max
mA/channel max
mA max
μA max
μA max
mW max
Test Conditions/Comments
Sinking 200 μA
Sourcing 200 μA
SDO only
SDO only
I
SINK
= 3 mA
I
SINK
= 6 mA
Outputs unloaded, Boost off. 0.25 mA/channel typ
Outputs unloaded, Boost on. 0.325 mA/channel typ
V
IH
= DV
DD
, V
IL
= DGND.
Typically 200 nA
Typically 3 μA
Outputs unloaded, Boost off, AV
DD
= DV
DD
= 3 V
1
AD5383-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.
2
Accuracy guaranteed from V
OUT
= 10 mV to AV
DD
– 50 mV.
3
Guaranteed by characterization, not production tested.
4
Default on the AD5383-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5383 control register; operating the AD5383-3 with a 2.5 V reference will lead to degraded
accuracy specifications and limited input code range.
AC CHARACTERISTICS
1
Table 5. AV
DD
= 4.5 V to 5.5 V; DV
DD
= 2.7 V to 5.5 V; AGND = DGND= 0 V
Parameter
All
Unit
DYNAMIC PERFORMANCE
Output Voltage Settling Time
2
6
μs typ
8
μs max
Slew Rate
2
2
V/μs typ
3
V/μs typ
Digital-to-Analog Glitch Energy
12
nV-s typ
Glitch Impulse Peak Amplitude
15
mV typ
Channel-to-Channel Isolation
100
dB typ
DAC-to-DAC Crosstalk
1
nV-s typ
Digital Crosstalk
0.8
nV-s typ
Digital Feedthrough
0.1
nV-s typ
Output Noise 0.1 Hz to 10 Hz
15
μV p-p typ
40
μV p-p typ
Output Noise Spectral Density
@ 1 kHz
150
nV/√Hz typ
@ 10 kHz
100
nV/√Hz typ
Test Conditions/Comments
1/4 scale to 3/4 scale change settling to ±1 LSB.
Boost mode off, CR9 = 0
Boost mode on, CR9 = 1
See Terminology section
See Terminology section
Effect of input bus activity on DAC output under test
External reference, midscale loaded to DAC
Internal reference, midscale loaded to DAC
1
Guaranteed by design and characterization, not production tested.
2
The slew rate can be programmed via the current boost control bit (CR9) in the AD5383 control register.
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