參數(shù)資料
型號： EVAL-AD5383EB
廠商： Analog Devices, Inc.
英文描述： 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
中文描述： 32通道，3伏/ 5 V，單電源，12位，電壓輸出DAC
文件頁數(shù)： 21/40頁
文件大小： 1201K
代理商： EVAL-AD5383EB
AD5383
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5383 is a complete, single-supply, 32-channel voltage
output DAC that offers 12-bit resolution. The part is available in
a 100-lead LQFP package and features both a parallel and a
serial interface. This product includes an internal, software
selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to
drive the buffered reference inputs; alternatively, an external
reference can be used to drive these inputs. Internal/external
reference selection is via the CR8 bit in the control register;
CR10 selects the reference magnitude if the internal reference is
selected. All channels have an on-chip output amplifier with
rail-to-rail output capable of driving 5 k in parallel with a
200 pF load.
Rev. 0 | Page 21 of 40
0
V
OUT
R
R
12-BIT
DAC
DAC
REG
m REG
c REG
×1 INPUT
REG
×2
INPUT DATA
V
REF
AVDD
Figure 27. Single-Channel Architecture
The architecture of a single DAC channel consists of a 12-bit
resistor-string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor-string architecture
guarantees DAC monotonicity. The 12-bit binary digital code
loaded to the DAC register determines at what node on the
string the voltage is tapped off before being fed to the output
amplifier. Each channel on these devices contains independent
offset and gain control registers that allow the user to digitally
trim offset and gain. These registers give the user the ability to
calibrate out errors in the complete signal chain, including the
DAC, using the internal m and c registers, which hold the
correction factors. All channels are double buffered, allowing
synchronous updating of all channels using the LDAC pin.
Figure 27 shows a block diagram of a single channel on the
AD5383. The digital input transfer function for each DAC can
be represented as
x2
= [(
m
+ 2)/ 2
n
×
x1
] + (
c
– 2
n
– 1
)
where:
x2
= the data-word loaded to the resistor string DAC.
x1
= the 12-bit data-word written to the DAC input register.
m
= the gain coefficient (default is 0xFFE). The gain coefficient
is written to the 11 most significant bits (DB11 to DB1) and the
LSB (DB0) is 0.
n
= DAC resolution (
n
= 12 for AD5383).
c
is the12-bit offset coefficient (default is 0x800).
The complete transfer function for these devices can be
represented as
V
OUT
= 2 ×
V
REF
×
x2
/2
n
x2
is the data-word loaded to the resistor string DAC.
V
REF
is the
internal reference voltage or the reference voltage externally
applied to the DAC REFOUT/REFIN pin. For specified
performance, an external reference voltage of 2.5 V is
recommended for the AD5380-5 and 1.25 V for the AD5380-3.
DATA DECODING
The AD5383 contains a 12-bit data bus, DB11–DB0. Depending
on the value of REG1 and REG0 (see Table 11), this data is
loaded into the addressed DAC input registers, offset (c)
registers, or gain (m) registers. The format data, offset (c), and
gain (m) register contents are shown in Table 12 to Table 14.
Table 11. Register Selection
REG1
REG0
Register Selected
1
1
Input Data Register (x1)
1
0
Offset Register (c)
0
1
Gain Register (m)
0
0
Special Function Registers (SFRs)
Table 12. DAC Data Format (REG1 = 1, REG0 = 1)
DB11 to DB0
1111
1111
1111
1111
1111
1110
1000
0000
0001
1000
0000
0000
0111
1111
1111
0000
0000
0001
0000
0000
0000
DAC Output (V)
2 V
REF
× (4095/4096)
2 V
REF
× (4094/4096)
2 V
REF
× (2049/4096)
2 V
REF
× (2048/4096)
2 V
REF
× (2047/4096)
2 V
REF
× (1/4096)
0
Table 13. Offset Data Format (REG1 = 1, REG0 = 0)
DB11 to DB0
1111
1111
1111
1111
1111
1110
1000
0000
0001
1000
0000
0000
0111
1111
1111
0000
0000
0001
0000
0000
0000
Offset (LSB)
+2048
+2047
+1
0
–1
–2047
–2048
Table 14. Gain Data Format (REG1 = 0, REG0 = 1)
DB11 to DB1
1111
1111
1011
1111
0111
1111
0011
1111
0000
0000
Gain Factor
1
0.75
0.5
0.25
0
1110
1110
1110
1110
0000
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