參數(shù)資料
型號： EP7211-CP-A
廠商： CRYSTAL SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： MULTIFUNCTION PERIPHERAL, PBGA256
封裝： PLASTIC, BGA-256
文件頁數(shù)： 89/166頁
文件大小： 2623K
代理商： EP7211-CP-A
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
89
Register Descriptions
DS352PP3
JUL 2001
5
PC
CARD1
: Enable for the interface to the CL-PS6700 device for PC Card slot 1. The main effect of this
bit is to reassign the functionality of Port B, Bit 0 to the
PRDY
input from the
CL-PS6700 devices, and to ensure that any access to the
NCS4
address space will be according to the
CL-PS6700 interface protocol.
6
PC
CARD2
: Enable for the interface to the CL-PS6700 device for PC Card slot 2. The main effect of this
bit is to reassign the functionality of Port B, Bit 1 to the
PRDY
input from the
CL-PS6700 devices, and to ensure that any access to the
NCS5
address space will be according to the
CL-PS6700 interface protocol.
8
UART2EN
: Internal UART2 enable bit. Setting this bit enables the internal UART2.
9
SS2MAEN
: Master mode enable for the synchronous serial interface 2. When low, SSI2 will be configured
for slave mode operation. When high, SSI2 will be configured for master mode operation. This bit also con-
trols the directionality of the interface pins.
12
OSTB
: This bit (operating system timing bit) is for use only with the 13 MHz clock source mode. Normally
it will be set low, however when set high it will cause a 500 kHz clock to be generated for the timers instead
of the 541 kHz which would normally be available. The divider to generate this frequency is not clocked
when this bit is set low.
13
CLKENSL
:
CLKEN
select. When low, the
CLKEN
signal will be output on the
RUN/CLKEN
pin. When
high, the
RUN
signal will be output on
RUN/CLKEN
.
14
BUZFREQ
: The BUZFREQ bit is used to select which hardware source will be used as the source to drive
the buzzer output pin. When BUZFREQ = 0, the buzzer signal generated from the on-chip timer (TC1) is
output. When BUZFREQ = 1, a fixed frequency clock is output
(500 Hz when running from the PLL, 528 Hz in the 13 MHz external clock mode). See the BZMOD and the
BZTOG bits for more details.
Bit
Description
相關(guān)PDF資料
PDF描述
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7309 HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7211-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-D 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP7212 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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