參數(shù)資料
型號： EP7211-CP-A
廠商： CRYSTAL SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： MULTIFUNCTION PERIPHERAL, PBGA256
封裝： PLASTIC, BGA-256
文件頁數(shù)： 38/166頁
文件大?。?/td> 2623K
代理商： EP7211-CP-A
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
38
Functional Description
DS352PP3
JUL 2001
3.3.1
Interrupt Latencies in Different States
3.3.1.1
Operating State
The ARM720T processor checks for a low level on its FIQ/IRQ inputs at the end of each instruction.
First, there is a one to two clock cycle synchronization penalty. For the case where the EP7211 is
operating at 13 MHz with a 16-bit external memory system, and instruction sequence stored in one
wait state Flash memory, the worst case interrupt latency is 251 clock cycles. This corresponds to the
processor executing a STM instruction to DRAM, and where the MMU needs to fetch protection/
translation information from page tables in DRAM memory. This includes a delay for cache line fills
for instruction prefetches, and a data abort occurring at the end of the LDM instruction, and the LDM
being non-quad word aligned. In addition, the worst-case interrupt latency assumes that LCD DMA
cycles to support a panel size of 320
x
240 at 4 bits-per-pixel, 60 Hz refresh rate, is in progress.
IRQ
12
UTXINT1
Internal UART1 transmit FIFO empty interrupt
IRQ
13
URXINT1
Internal UART1 receive FIFO full interrupt
IRQ
14
UMSINT
Internal UART1 modem status changed interrupt
IRQ
15
SSEOTI
Synchronous serial interface 1 end of transfer interrupt
Table 3-2. Interrupt Allocation in Second Interrupt Register
Interrupt
Bit in INTMR2
and INTSR2
Name
Comment
IRQ
0
KBDINT
Key press interrupt
IRQ
1
SS2RX
Master/slave SSI 16 bytes received
IRQ
2
SS2TX
Master/slave SSI 16 bytes transmitted
IRQ
12
UTXINT2
UART2 transmit FIFO empty interrupt
IRQ
13
URXINT2
UART2 receive FIFO full interrupt
Table 3-3. Interrupt Allocation in Third Interrupt Register
Interrupt
Bit in INTMR3
and INTSR3
Name
Comment
FIQ
0
MCPINT
MCP interface interrupt
Table 3-1. Interrupt Allocation in First Interrupt Register
(cont.)
Interrupt
Bit in INTMR1
and INTSR1
Name
Comment
相關(guān)PDF資料
PDF描述
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7309 HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7211-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-D 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP7212 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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